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Introduction

Principle of Operation

Each of the 32 channels of the PETIROC-2A has a fast time discriminator. The ASIC drives one trigger line per channel plus two chip-level OR outputs (time OR and charge OR). On the DT5550W those lines arrive at the FPGA and are made available to a SciCompiler design through this block.

The block generates no hardware. CompileHDL does not instantiate any entity and writes no .vhd: it calls GenerateServiceHDL and then emits one plain concurrent assignment per connected pin, binding the pin’s net to the board-support signal of the selected ASIC:

vhdl 
  -- outputs (one line per connected pin)
<net of TRIG0>     <= A_TRIG0;
<net of OR_TIME>   <= A_OR_TIME;
<net of OR_CHARGE> <= A_OR_CHARGE;
<net of TRIGs>     <= A_TRIGs;
-- inputs
TRIGGER_EXT_A_s    <= <net of TRIGGER_EXT>;

The A_ prefix is the ASIC property (A, B, C, D). Because the block is a pure alias, it costs no logic, adds no latency and introduces no register stage: whatever the board wrapper presents is what the pin carries, in the same clock cycle.

Pins you leave unconnected are skipped entirely (the generator checks UsingOpenOrDefaultConnection), so an unused trigger pin emits no assignment and no dangling net.

Pin Description

TRIGGER_EXT Input 1 bit BIT
External trigger to the ASIC – driven into the board signal TRIGGER_EXT_<ASIC>_s, which reaches an ASIC external-trigger pad. Use it to force a conversion from the design (software pulse, LEMO input, coincidence between two chips). Leave it open if the ASIC is to trigger only on its own discriminators - an unconnected pin emits no assignment at all and the board signal keeps its default '0'. See the alert in the description about the crossed A↔D / B↔C mapping.
Default: 0
TRIG0 Output 1 bit BIT
Channel 0 fast trigger – active-high copy of the ASIC’s channel-0 time discriminator (not A_TRG(0) at board level). Combinational, no register stage. Identical to TRIGs(0).
TRIG1 Output 1 bit BIT
Channel 1 fast trigger – see TRIG0. Identical to TRIGs(1).
TRIG2 Output 1 bit BIT
Channel 2 fast trigger – see TRIG0. Identical to TRIGs(2).
TRIG3 Output 1 bit BIT
Channel 3 fast trigger – see TRIG0. Identical to TRIGs(3).
TRIG4 Output 1 bit BIT
Channel 4 fast trigger – see TRIG0. Identical to TRIGs(4).
TRIG5 Output 1 bit BIT
Channel 5 fast trigger – see TRIG0. Identical to TRIGs(5).
TRIG6 Output 1 bit BIT
Channel 6 fast trigger – see TRIG0. Identical to TRIGs(6).
TRIG7 Output 1 bit BIT
Channel 7 fast trigger – see TRIG0. Identical to TRIGs(7).
TRIG8 Output 1 bit BIT
Channel 8 fast trigger – see TRIG0. Identical to TRIGs(8).
TRIG9 Output 1 bit BIT
Channel 9 fast trigger – see TRIG0. Identical to TRIGs(9).
TRIG10 Output 1 bit BIT
Channel 10 fast trigger – see TRIG0. Identical to TRIGs(10).
TRIG11 Output 1 bit BIT
Channel 11 fast trigger – see TRIG0. Identical to TRIGs(11).
TRIG12 Output 1 bit BIT
Channel 12 fast trigger – see TRIG0. Identical to TRIGs(12).
TRIG13 Output 1 bit BIT
Channel 13 fast trigger – see TRIG0. Identical to TRIGs(13).
TRIG14 Output 1 bit BIT
Channel 14 fast trigger – see TRIG0. Identical to TRIGs(14).
TRIG15 Output 1 bit BIT
Channel 15 fast trigger – see TRIG0. Identical to TRIGs(15).
TRIG16 Output 1 bit BIT
Channel 16 fast trigger – see TRIG0. Identical to TRIGs(16).
TRIG17 Output 1 bit BIT
Channel 17 fast trigger – see TRIG0. Identical to TRIGs(17).
TRIG18 Output 1 bit BIT
Channel 18 fast trigger – see TRIG0. Identical to TRIGs(18).
TRIG19 Output 1 bit BIT
Channel 19 fast trigger – see TRIG0. Identical to TRIGs(19).
TRIG20 Output 1 bit BIT
Channel 20 fast trigger – see TRIG0. Identical to TRIGs(20).
TRIG21 Output 1 bit BIT
Channel 21 fast trigger – see TRIG0. Identical to TRIGs(21).
TRIG22 Output 1 bit BIT
Channel 22 fast trigger – see TRIG0. Identical to TRIGs(22).
TRIG23 Output 1 bit BIT
Channel 23 fast trigger – see TRIG0. Identical to TRIGs(23).
TRIG24 Output 1 bit BIT
Channel 24 fast trigger – see TRIG0. Identical to TRIGs(24).
TRIG25 Output 1 bit BIT
Channel 25 fast trigger – see TRIG0. Identical to TRIGs(25).
TRIG26 Output 1 bit BIT
Channel 26 fast trigger – see TRIG0. Identical to TRIGs(26).
TRIG27 Output 1 bit BIT
Channel 27 fast trigger – see TRIG0. Identical to TRIGs(27).
TRIG28 Output 1 bit BIT
Channel 28 fast trigger – see TRIG0. Identical to TRIGs(28).
TRIG29 Output 1 bit BIT
Channel 29 fast trigger – see TRIG0. Identical to TRIGs(29).
TRIG30 Output 1 bit BIT
Channel 30 fast trigger – see TRIG0. Identical to TRIGs(30).
TRIG31 Output 1 bit BIT
Channel 31 fast trigger – see TRIG0. Identical to TRIGs(31).
OR_TIME Output 1 bit BIT
Time OR – high while any of the 32 time discriminators is over threshold. The board computes it as not and_reduce(A_TRG), i.e. an OR over the active-low per-channel triggers; it is not a coincidence output. This is the usual trigger source for the Petiroc Digital block.
OR_CHARGE Output 1 bit BIT
Charge OR – active-high copy of the ASIC’s charge-OR output (not OR_CHARGE_A at board level). Fires on the charge branch rather than the time branch; typical trigger source for the Petiroc Analog block.
TRIGs Output 32 bit BIT VECTOR
Trigger bus – all 32 channel triggers in one active-high vector, TRIGs(i) = TRIG<i>. Convenient for multiplicity counting, hit-pattern histogramming or masking whole groups of channels in one expression.

Properties

Property window

ASIC ASIC

Select the ASIC to be connected to the Endpoint

Selects which of the four PETIROC-2A chips of the DT5550W this block is bound to. The value is pasted verbatim into every emitted assignment, so A produces A_TRIG0, A_OR_TIME, TRIGGER_EXT_A_s and so on.

Value Board signal prefix
A A_* / TRIGGER_EXT_A_s
B B_* / TRIGGER_EXT_B_s
C C_* / TRIGGER_EXT_C_s
D D_* / TRIGGER_EXT_D_s

The property is marked isVisible = False: it is not shown in the property grid, the board plug-in assigns it when the block is placed on a given ASIC. Changing it does not rebuild the symbol (RedesignIfChanged = False) because the pin list is the same for all four chips.

Default: A

Default: A

Options: A B C D

⚙️ Detailed Operation

What the board wrapper puts on these signals

The DT5550W-PETIROC board support file (dt5550w_top.vht) builds the signals this block reads. The ASIC’s trigger outputs are active low; the board inverts them, so every pin of this block is active high:

Block pin Board signal Board expression
TRIG0 … TRIG31 A_TRIG0 … A_TRIG31 A_TRIGn(0) <= not A_TRG(n);
TRIGs A_TRIGs A_TRIGs <= not A_TRG;
OR_TIME A_OR_TIME A_OR_TIME(0) <= not and_reduce(A_TRG);
OR_CHARGE A_OR_CHARGE A_OR_CHARGE(0) <= not OR_CHARGE_A;
TRIGGER_EXT TRIGGER_EXT_A_s drives an ASIC *_TRIG_EXT pad

Two consequences worth noting:

  • TRIGs and the 32 individual TRIG<i> pins carry exactly the same information. TRIGs(i) and TRIG<i> are driven from the same A_TRG(i) bit. Use the bus when you want to feed a multiplicity counter or a hit pattern, the individual pins when you want to wire a single channel.
  • OR_TIME is not and_reduce(A_TRG), i.e. the OR of the 32 active-low channel triggers: it is high as soon as any channel fires. It is not a coincidence/AND output.

Typical use 

   Petiroc Trigger                     rest of the design
┌───────────────┐
│      TRIG0 ───┼──► per-channel rate counter
│        …      │
│     TRIG31 ───┤
│      TRIGs ───┼──► multiplicity / hit pattern
│    OR_TIME ───┼──► "Petiroc Digital" TRIG   (start a readout)
│  OR_CHARGE ───┼──► "Petiroc Analog"  TRIG
│               │
│ TRIGGER_EXT ◄─┼──  software / LEMO / coincidence logic
└───────────────┘

OR_TIME (any channel over the time threshold) is the natural trigger source for Petiroc Digital, which starts the ASIC conversion and reads back the TDC/ADC frame. TRIGGER_EXT goes the other way: it lets the design force a conversion on the ASIC independently of its internal discriminators.

One instance per ASIC

The block is bound to a single ASIC through the hidden ASIC property, which the board plug-in sets when the component is placed. Four instances (A, B, C, D) give access to all four PETIROC chips of a DT5550W. Two instances that resolve to the same ASIC letter would emit two drivers on the same board signal - place one instance per ASIC.

Failure modes

This block cannot fail at compile time: it has no generics, no resource file and no validation. The only message it prints is the informational

  Generating HDL code For <designator>

If a pin appears dead, the cause is upstream of the block (the ASIC’s discriminators are configured through Petiroc Slow Control - trigger thresholds, per-channel masks and the 10-bit DACs all live in the 640-bit configuration bitstream).