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Introduction

This block implements a single-port RAM where read and write operations share the same address port. Write operations occur when WR=1; read operations occur when WR=0.

Read latency: 1 clock cycle (registered output).

Pin Description

IN Input Variable bit BIT
Input data to write. Width: Bit Width (1-1024 bits).
Default: Must be connected
ADDR Input 16 bit BIT VECTOR
Address for read/write operations. Width: 16 bits. Valid range: 0 to Memory Size-1.
Default: Must be connected
WR Input 1 bit BIT
Write enable (1-bit). When 1, writes IN to ADDR. When 0, reads from ADDR to OUT.
Default: Must be connected
CLK Input 1 bit BIT
Clock signal for synchronous operation.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset (resets pointers, not RAM contents).
Default: Must be connected
OUT Output Variable bit BIT
Output data from read operations. Width: Bit Width. Latency: 1 clock cycle.

Properties

Property window

Memory Size MemorySize

Set the amount of memory in number of words

Number of words in RAM. Allowed: 64-65536. Determines address range.

Default: 1024

Options: 64 128 256 512 1024 2048 4096 8192 16384 32756 65536

Bit Width BusWidth

Set the size in bits of the data

Bit width per word. Range: 1-1024. Total RAM = MemorySize × BusWidth bits.

Default: 1

Range: 1 – 1024

Functional description

Single-port RAM uses one address port for both read and write:

  • When WR=1: Writes IN data to address ADDR
  • When WR=0: Reads data from address ADDR to OUT (1 cycle later)

Cannot read and write simultaneously to different addresses.

Timing

Write: Data written on rising edge when WR=1. Read: Data available 1 cycle after ADDR provided with WR=0.

Typical use cases

  • Simple data storage
  • Lookup tables
  • Small buffers