Xilinx
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Introduction

Identical to Convolution (triggered, fixed kernel) except the kernel coefficients live in a RAM inside the IP:

  • drive COEF_ADDR with the tap index (0 .. K-1),
  • drive COEF_DATA with the signed coefficient,
  • pulse COEF_LOAD for one clock to latch it.

Coefficient writes are honoured on every clock, in any state; avoid rewriting coefficients while BUSY = 1 if you need a coherent kernel for the acquisition in progress.

$$ y[p] = \sum_{m} x[m] \cdot h[p-m], \quad p = 0 \ldots 2K-2 $$

Pin Description

IN Input InputSize bit BIT VECTOR
Signed input samples. Sampled during COLLECT only.
Default: Must be connected
START Input 1 bit BIT
Trigger, rising-edge sensitive. Ignored while BUSY=1.
Default: Must be connected
COEF_ADDR Input ceil(log2(K)) bit BIT VECTOR
Coefficient write address (tap index 0..K-1).
COEF_DATA Input CoefSize bit BIT VECTOR
Coefficient write data (signed).
COEF_LOAD Input 1 bit BIT
One-clock pulse: latches COEF_DATA into ram[COEF_ADDR].
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
OUT Output InputSize+CoefSize+ceil(log2(K)) bit BIT VECTOR
Convolution point y[p]. Signed. Valid when DV=1.
INDEX Output ceil(log2(2K-1)) bit BIT VECTOR
Index p of the point on OUT (0 .. 2K-2). Valid when DV=1.
DV Output 1 bit BIT
One-clock pulse for every produced convolution point.
FIRST Output 1 bit BIT
Pulses with the first point (p=0).
LAST Output 1 bit BIT
Pulses with the last point (p=2K-2).
BUSY Output 1 bit BIT
High from START to LAST.

Properties

Property window

Input Bit Width InputSize

Bit width of the signed input samples.

Bit width of the signed input samples: 16, 24 or 32.

Default: 16

Options: 16 24 32

Coefficient Bit Width CoefSize

Bit width of each kernel coefficient (signed). Width of the COEF_DATA input.

Bit width of each kernel coefficient (signed), 8..32. Width of COEF_DATA.

Default: 16

Options: 8 10 12 14 16 18 20 24 28 32

Kernel Length KernelLen

Number of kernel coefficients K (coefficient RAM depth). The IP captures K samples after START.

Number of kernel coefficients K (2..4096) = coefficient RAM depth.

Default: 64

Range: 2 – 4096

Parallel MACs ParallelMacs

Number of parallel MAC units P (1 .. KernelLen, clamped to KernelLen at compile time). Each convolution point takes ceil(K/P) clocks, the whole graph ~ (2K-1)*ceil(K/P) clocks plus the 2K-1 clock output burst. Cost: P multipliers and P memory banks.

Number of parallel MAC units P (1..K, clamped to KernelLen at compile time). Each convolution point takes $\lceil K/P \rceil$ clocks, so the full graph costs about $(2K-1)\cdot\lceil K/P \rceil$ clocks plus the $2K-1$ clock output burst. Cost: P multipliers (DSP), P input-buffer banks and P private copies of the coefficient RAM (each COEF_LOAD write goes to all copies), so memory grows with P as well.

Default: 1

Range: 1 – 4096

Loading the kernel

text 
  for k in 0 .. K-1:
    COEF_ADDR <= k
    COEF_DATA <= h[k]
    COEF_LOAD <= 1 for one clock

Coefficients not written default to 0 after configuration.

Operation and timing

Same as the fixed variant: COLLECT (K clocks) then COMPUTE (~K*(2K-1) clocks with one MAC), each finished point streamed with DV=1, FIRST at p=0, LAST at p=2K-2, BUSY high outside IDLE.

Output width

$$ \text{OUT_BITS} = \text{InputSize} + \text{CoefSize} + \lceil \log_2 K \rceil $$