Xilinx
Block Preview

Introduction

For every requested lag $k$, the block computes

$$ R[k] = \sum_{\substack{0 \le n < \text{WIN_LEN} \ 0 \le n-k < \text{WIN_LEN}}} X[n] \cdot Y[n-k] $$

and outputs it as a stream of $2 \cdot \text{LAG_RANGE} + 1$ bins, in order $k = -\text{LAG_RANGE}, \ldots, 0, \ldots, +\text{LAG_RANGE}$.

Unlike the real-time single-lag block, this component is not throughput- bound: after a trigger it “takes as long as it needs” (typically a few million clocks for a 1k-sample window with 128 lags) but only requires a handful of MAC resources (one product per clock, II=1).

Pin Description

X_IN Input InputSize bit BIT VECTOR
First signed input sample. Only sampled during COLLECT.
Default: Must be connected
Y_IN Input InputSize bit BIT VECTOR
Second signed input sample. Only sampled during COLLECT.
Default: Must be connected
START Input 1 bit BIT
Trigger, rising-edge sensitive. A 0->1 transition initiates a new correlogram acquisition. Ignored while BUSY = 1.
Default: Must be connected
WIN_LEN Input 11 bit BIT VECTOR
Effective window length (samples captured per trigger). Range: 1 .. WindowMax. Treat as ap_stable (do not change during BUSY).
Default: Must be connected
LAG_RANGE Input 9 bit BIT VECTOR
Effective lag range. The block outputs 2*LAG_RANGE+1 bins covering k = -LAG_RANGE .. +LAG_RANGE. Range: 0 .. LagMax. Treat as ap_stable.
Default: Must be connected
CLK Input 1 bit BIT
Clock. All logic operates on the rising edge.
Default: Default Board Clock
R_OUT Output AccumBits bit BIT VECTOR
Current correlogram bin R[k]. Signed, AccumBits wide. Valid on DV=1.
LAG_OUT Output LagBits+1 bit BIT VECTOR
Signed lag index corresponding to R_OUT. Width = ceil(log2(LagMax+1)) + 1 bits. Range: -LAG_RANGE .. +LAG_RANGE.
DV Output 1 bit BIT
Data valid, active high. Asserted while streaming R_OUT/LAG_OUT.
FIRST Output 1 bit BIT
Pulses high for one clock on the very first output bin (k = -LAG_RANGE).
LAST Output 1 bit BIT
Pulses high for one clock on the very last output bin (k = +LAG_RANGE).
BUSY Output 1 bit BIT
High whenever the block is not in IDLE (COLLECT, COMPUTE or OUTPUT). Use it to gate downstream logic or to know when a new START can be issued.

Properties

Property window

Input Bit Width InputSize

Bit width of the signed X and Y input samples

Bit width of X and Y (signed). 4..32 bits.

Default: 16

Range: 4 – 32

Max Window (WIN_MAX) WindowMax

Maximum runtime value of WIN_LEN. Sizes the two X/Y capture BRAMs (each holds WindowMax samples of InputSize bits).

Maximum runtime value of WIN_LEN. Sizes the X and Y capture BRAMs (each WindowMax * InputSize bits). This is the dominant memory cost.

Default: 1024

Options: 128 256 512 1024 2048 4096 8192 16384

Max Lag Range (LAG_MAX) LagMax

Maximum runtime value of LAG_RANGE. Correlogram will hold up to 2*LagMax+1 output bins (BRAM).

Maximum runtime value of LAG_RANGE. Correlogram output can be up to 2*LagMax + 1 bins long. Also sizes the R output BRAM ((2*LagMax + 1) * AccumBits bits).

Default: 256

Options: 16 32 64 128 256 512 1024 2048

Accumulator Bits AccumBits

Bit width of R_OUT and per-lag accumulator (signed).

Bit width of R_OUT and the per-lag accumulator (signed). Should satisfy AccumBits >= 2*InputSize + ceil(log2(WindowMax)) to guarantee no overflow.

Default: 48

Range: 16 – 96

Functional description

Four states

  • IDLE — waiting for START to go high.
  • COLLECT — captures WIN_LEN samples of X and Y into two separate BRAMs. Duration: WIN_LEN clocks.
  • COMPUTE — for every lag $k$ from $-\text{LAG_RANGE}$ to $+\text{LAG_RANGE}$, iterates $n = 0..\text{WIN_LEN}-1$ and accumulates the products where both $n$ and $n - k$ fall inside the window. Duration: approximately $\text{WIN_LEN} \cdot (2 \cdot \text{LAG_RANGE} + 1)$ clocks. Inner loop is II=1.
  • OUTPUT — streams the correlogram out one bin per clock with DV, FIRST, LAST handshake.

BUSY is high in every state except IDLE.

Boundary handling

Samples outside the captured window are treated as zero (equivalent to a rectangular data window). At $|k| = \text{WIN_LEN}$ the sum is empty and $R[k] = 0$.

Memory

  • X buffer: BRAM of depth WindowMax, entries InputSize bits.
  • Y buffer: BRAM of depth WindowMax, entries InputSize bits.
  • R buffer: BRAM of depth 2*LagMax + 1, entries AccumBits bits.

The R buffer lets the block finish computing before streaming out, so the downstream logic sees a clean, back-pressure-free stream.

Retrigger

Do not raise START again while BUSY = 1 — the state machine ignores edges during COLLECT/COMPUTE/OUTPUT. Wait for LAST (or watch BUSY fall) before starting a new acquisition.