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Introduction

This block converts between signed and unsigned binary representations while optionally changing the bit width. It implements proper sign extension, zero extension, and truncation based on the selected conversion mode.

The operation is purely combinational with zero clock latency. Four conversion modes are supported:

  • Unsigned → Unsigned: Bit width change only (zero extend/truncate)
  • Signed → Signed: Bit width change with sign extension/truncate
  • Unsigned → Signed: Add sign bit interpretation
  • Signed → Unsigned: Remove sign bit interpretation

Pin Description

a Input 16 bit BIT VECTOR
b Output 16 bit BIT VECTOR
IN Variable bit
Input binary signal, always std_logic_vector. Width: Configurable via Input bits property (2 to 2048 bits) Interpretation: Configurable via Input sign property (UNSIGNED or SIGNED)
Default: Must be connected
OUT Variable bit

Output binary signal, always std_logic_vector. Width: Configurable via Out bits property (2 to 2048 bits) Interpretation: Configurable via Output sign property (UNSIGNED or SIGNED)

Output is combinational (zero latency). Conversion mode is determined by the combination of input/output sign settings.

Properties

Property window

Input bits InputSize

Set the number of bits of the input

Number of bits in the input signal (2 to 2048 bits).

Default: 16

Range: 2 – 2048

Input sign InputSign

Select the sign/unsign of the input

Interpretation of input signal: UNSIGNED (0 to 2^N-1) or SIGNED (two’s complement, -2^(N-1) to 2^(N-1)-1).

Default: UNSIGNED

Options: UNSIGNED SIGNED

Out bits OutputSize

Set the number of bits of the output

Number of bits in the output signal (2 to 2048 bits). Can be different from input size.

Default: 16

Range: 2 – 2048

Output sign OutputSign

Select the sign/unsign of the output

Interpretation of output signal: UNSIGNED (0 to 2^N-1) or SIGNED (two’s complement, -2^(N-1) to 2^(N-1)-1).

Default: UNSIGNED

Options: UNSIGNED SIGNED

Functional description

The component performs binary representation conversion with four distinct modes:

1. Unsigned to Unsigned (width change)

Simple bit width adjustment:

  • Expansion ($N_\text{out} > N_\text{in}$): Zero-extend MSBs $$ \mathrm{OUT}[N_\text{out}-1:N_\text{in}] = 0 $$ $$ \mathrm{OUT}[N_\text{in}-1:0] = \mathrm{IN}[N_\text{in}-1:0] $$
  • Truncation ($N_\text{out} < N_\text{in}$): Keep LSBs only $$ \mathrm{OUT}[N_\text{out}-1:0] = \mathrm{IN}[N_\text{out}-1:0] $$

2. Signed to Signed (width change)

Bit width adjustment with sign extension:

  • Expansion ($N_\text{out} > N_\text{in}$): Sign-extend MSBs $$ \mathrm{OUT}[N_\text{out}-1:N_\text{in}] = \mathrm{IN}[N_\text{in}-1] $$ $$ \mathrm{OUT}[N_\text{in}-1:0] = \mathrm{IN}[N_\text{in}-1:0] $$
  • Truncation ($N_\text{out} < N_\text{in}$): Keep LSBs, may lose sign $$ \mathrm{OUT}[N_\text{out}-1:0] = \mathrm{IN}[N_\text{out}-1:0] $$

3. Unsigned to Signed

Reinterpret unsigned value as signed (adds sign bit):

  • Input represents: $0$ to $2^{N_\text{in}} - 1$
  • If $N_\text{out} > N_\text{in}$: Zero-extend (preserves value)
  • If $N_\text{out} = N_\text{in}$: Values $\geq 2^{N_\text{in}-1}$ become negative
  • Output represents: $-2^{N_\text{out}-1}$ to $2^{N_\text{out}-1} - 1$

4. Signed to Unsigned

Reinterpret signed value as unsigned (removes sign bit interpretation):

  • Input represents: $-2^{N_\text{in}-1}$ to $2^{N_\text{in}-1} - 1$
  • Negative values become large positive values (preserve bit pattern)
  • If $N_\text{out} > N_\text{in}$: Sign-extend then reinterpret
  • Output represents: $0$ to $2^{N_\text{out}} - 1$

Conversion examples

Unsigned to Signed (8-bit to 16-bit):

  • IN = 0x7F (127 unsigned) → OUT = 0x007F (127 signed)
  • IN = 0xFF (255 unsigned) → OUT = 0x00FF (255 signed)

Unsigned to Signed (8-bit to 8-bit):

  • IN = 0x7F (127 unsigned) → OUT = 0x7F (127 signed)
  • IN = 0xFF (255 unsigned) → OUT = 0xFF (-1 signed, reinterpretation!)

Signed to Unsigned (8-bit to 8-bit):

  • IN = 0x7F (127 signed) → OUT = 0x7F (127 unsigned)
  • IN = 0xFF (-1 signed) → OUT = 0xFF (255 unsigned, reinterpretation!)

Signed to Signed (8-bit to 16-bit, sign extension):

  • IN = 0x7F (127) → OUT = 0x007F (127)
  • IN = 0xFF (-1) → OUT = 0xFFFF (-1, sign extended)

Signed truncation (16-bit to 8-bit):

  • IN = 0x007F (127) → OUT = 0x7F (127)
  • IN = 0xFFFF (-1) → OUT = 0xFF (-1)
  • IN = 0x0180 (384) → OUT = 0x80 (-128, overflow!)

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Signed/Unsigned Conv 0

Output is available immediately in the same clock cycle.

Typical use cases

  • Converting ADC outputs (unsigned) to signed for offset correction
  • Interfacing components with different signedness requirements
  • Bit width adjustment with proper sign handling
  • Removing DC offsets by converting unsigned to signed

Important notes

  • When converting unsigned→signed with same width, values ≥ $2^{N-1}$ become negative
  • When converting signed→unsigned, negative values become large positive values
  • Truncation can cause overflow (loss of significant bits)
  • Always ensure output width is sufficient to avoid data loss