Xilinx
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Introduction

Identical datapath to FFT Windowed (see that guide for operation, overlap rules and the CE duty limit), but the window is a 16-bit Q16 RAM instead of a compile-time ROM. Until loaded the window is rectangular (all ones). Write coefficient $w[n]$ by driving COEF_ADDR = n, COEF_DATA = round(w*65535) and pulsing COEF_WE for one clock; with overlap enabled the write is applied to both core RAMs at once. Load while the block is idle (before enabling the input stream) to avoid mixing windows inside one frame.

Use the FFT Windowed designer (on the fixed block) to preview a window and export the coefficient CSV (addr,coef per line) for your runtime loader.

Pin Description

DATA_IN Input 16 bit BIT VECTOR
16-bit signed samples, CE gated.
Default: Must be connected
CE Input 1 bit BIT
Clock enable, duty <= hop/N with overlap. Default ‘1’.
Default: 1
COEF_ADDR Input 10 bit BIT VECTOR
Window coefficient address, 0..N-1 (log2 N bits).
COEF_DATA Input 16 bit BIT VECTOR
Coefficient value, unsigned Q16 (65535 = 1.0).
COEF_WE Input 1 bit BIT
Write strobe, one clock per coefficient.
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
OUT_RE Output 32 bit BIT VECTOR
Real part of the spectrum bins (32 bit, unscaled).
OUT_IM Output 32 bit BIT VECTOR
Imaginary part.
DV Output 1 bit BIT
Bin valid.
FIRST Output 1 bit BIT
Pulse on bin 0 of each frame.
LAST Output 1 bit BIT
Pulse on bin N-1.
BUSY Output 1 bit BIT
Frame in progress.
OVERRUN Output 1 bit BIT
Missed frame boundary pulse.
START
Burst engines only: frame trigger (tie to 1 for auto restart).

Properties

Property window

FFT Length Length

Transform length N (power of 2)

Transform length N (128..16384, power of 2).

Default: 1024

Options: 128 256 512 1024 2048 4096 8192 16384

Algorithm Algorithm

Pipelined: continuous, no START pin. Radix-4/Radix-2/Radix-2 Lite: framed, needs START (tie ‘1’ for auto restart).

Pipelined (continuous, no START) or Radix-4 / Radix-2 / Radix-2 Lite (framed, START).

Default: Pipelined

Options: Pipelined Radix-4 Radix-2 Radix-2 Lite

Overlap Overlap

Frame overlap. None: 1 core. 25%/50%: two cores ping-pong. Max input CE duty = hop/N.

None / 25% / 50% (two cores with overlap, CE duty <= hop/N).

Default: None

Options: None 25% 50%