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Introduction

The subtractor performs binary subtraction between two input operands IN1 and IN2, producing the difference on output OUT.

$$ \mathrm{OUT} = \mathrm{IN1} - \mathrm{IN2} $$

The component supports both signed and unsigned arithmetic according to the Input sign property. An optional pipeline register can be enabled to improve timing at the cost of one clock cycle latency.

Pin Description

IN1 Input Variable bit BIT VECTOR
Minuend input (first operand). Width: Input bits (2 – 256). Arithmetic type set by Input sign.
Default: Must be connected
IN2 Input Variable bit BIT VECTOR
Subtrahend input (second operand). Width: Input bits (2 – 256). Arithmetic type set by Input sign.
Default: Must be connected
OUT Output Variable bit BIT VECTOR

Difference output. Width depends on Output Size property:

  • SAME INPUT: same as Input bits
  • EXTRA BIT: Input bits + 1
CLK 1 bit
Clock input. Only present when Register Output is enabled. Rising edge triggers output register update.
RESET 1 bit
Synchronous reset, active high. Only present when Register Output is enabled. Clears the output register to zero on the next rising clock edge.

Properties

Property window

Input bits InputSize

Set the number of bits of the input

Number of bits for both input operands IN1 and IN2. Range: 2 – 256. Determines the width of the subtractor datapath.

Default: 16

Range: 2 – 256

Output Size OutputSize

Select if the output should have one extra bit to avoid overflow in the result

Controls output bit width:

  • SAME INPUT: Output width equals Input bits (underflow wraps around)
  • EXTRA BIT: Output width is Input bits + 1 (sign extension included)

Default: SAME INPUT

Options: SAME INPUT EXTRA BIT

Input sign InputSign

Select the sign/unsign of the input

Selects arithmetic type for inputs and output:

  • UNSIGNED: Non-negative integers, range [0, 2^N-1]
  • SIGNED: Two’s-complement, range [-2^(N-1), 2^(N-1)-1]

Default: UNSIGNED

Options: UNSIGNED SIGNED

Register Output EnableRegister

Enable one pipeline stage adding a register. Improve system timing but increase pipeline delay from 0 to 1 clock cycle

Enables output pipeline register.

  • False: Combinatorial output (0 latency)
  • True: Registered output (1 cycle latency, improved timing)

Default: False

Protect Overflow ProtectOverflow

Enable overflow protection logic. The overflow logic will saturate output to maximum value in overflow condition. This option, if enabled, negatively impact on system timing.

Enables saturation logic on overflow/underflow.

  • False: Arithmetic wraps around on overflow
  • True: Output saturates to min/max value (impacts timing)

Default: False

Functional description

The subtractor implements a combinatorial or registered subtraction:

$$ y = a - b $$

where:

  • a → IN1 (minuend)
  • b → IN2 (subtrahend)
  • y → OUT (difference)

Output width options

The Output Size property controls the output bit width:

  • SAME INPUT: Output has the same width as inputs (wrap-around on underflow)
  • EXTRA BIT: Output has one extra bit to accommodate the sign extension

Overflow protection

When Protect Overflow is enabled, the output saturates to the minimum or maximum representable value instead of wrapping around. This option impacts timing performance.

Latency

The component latency depends on the Register Output property:

Register Output Latency (clock cycles)
Disabled 0 (combinatorial)
Enabled 1

Typical use cases

  • Difference calculation in DSP algorithms
  • Error signal generation in control loops
  • Baseline subtraction in signal processing
  • Delta encoding for data compression