Slice [TM]
Time-multiplexed bitwise slicing operation. Extracts a contiguous range of bits from the input binary word based on configurable start and stop bit indices. Supports TM factors from 2 to 32. Pure combinational logic (zero latency). Essential for bit field extraction and manipulation.
Introduction
This block performs a bit slicing operation on time-multiplexed (TM) data streams. It extracts a contiguous range of bits from the input word, specified by the Start Bit (MSB) and Stop Bit (LSB) properties.
The operation is purely combinational with zero clock latency:
$$ \mathrm{OUT}(n) = \mathrm{IN}(n)[\text{StartBit} : \text{StopBit}], $$
The TM Factor property determines how many parallel samples are processed per clock cycle.
Pin Description
Input binary data, always TM.
Width: Input Size × TM Factor
Each TM phase receives its corresponding slice of the input bus.
Bits are indexed from 0 (LSB) to Input Size - 1 (MSB).
Sliced output, always TM (same factor as IN).
Width: Output Size × TM Factor
Output Size = |Start Bit - Stop Bit| + 1
Output is combinational (zero latency). Contains the extracted bit range from IN.
Properties
Set the input word size in bits per phase
Number of bits per input sample ($N_\text{in}$). Range: 2 – 128. Each TM phase processes samples of this width.
Defines the total number of bits available for slicing.
Default: 16
Range: 2 – 128
Set the time multiplexing factor (number of phases)
Time-multiplexing factor (number of parallel phases). Allowed values: 2, 4, 8, 16, 32 (up to 32). Higher values increase throughput proportionally but consume more FPGA resources (one slice instance per TM phase).Default: 4
Range: 2 – 32
Slicing MSB (per phase)
MSB (most significant bit) of the extracted slice. Range: 0 – 127 (must be < Input Size and ≥ Stop Bit).
Together with Stop Bit, defines the extracted bit range. Start Bit is the leftmost (highest-indexed) bit of the output.
Default: 7
Range: 0 – 127
Slicing LSB (per phase)
LSB (least significant bit) of the extracted slice. Range: 0 – 127 (must be < Input Size and ≤ Start Bit).
Together with Start Bit, defines the extracted bit range. Stop Bit is the rightmost (lowest-indexed) bit of the output.
Output width = Start Bit - Stop Bit + 1.
Default: 0
Range: 0 – 127
Functional description
The component implements a bitwise slice in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.
For each TM phase, the operation extracts bits from the input:
$$ y[i] = x[i][\text{high} : \text{low}], $$
where:
- $x[i]$ → input sample at phase $i$ (width = Input Size)
- $y[i]$ → output sample at phase $i$ (width = |StartBit - StopBit| + 1)
- StartBit → MSB index of the slice
- StopBit → LSB index of the slice
Bit indexing
- Bit 0 = LSB (rightmost bit)
- Bit N-1 = MSB (leftmost bit) for N-bit input
- Start Bit ≥ Stop Bit (for standard extraction)
- Output width = |Start Bit - Stop Bit| + 1
Example
Given a 16-bit input 1010110011001100:
- Start Bit = 11, Stop Bit = 4 → Output (8 bits) =
10110011 - Start Bit = 7, Stop Bit = 0 → Output (8 bits) =
11001100(lower byte) - Start Bit = 15, Stop Bit = 8 → Output (8 bits) =
10101100(upper byte) - Start Bit = 5, Stop Bit = 5 → Output (1 bit) =
1(single bit extraction)
Mathematical background
Bit slicing can be expressed as a combination of right shift and masking:
$$ \text{OUT} = (x \gg \text{StopBit}) \text{ AND } (2^{W} - 1) $$
where $W$ = output width = |StartBit - StopBit| + 1.
This is commonly used for:
- Extracting bit fields from packed data structures
- Isolating specific portions of binary numbers
- Building communication protocol parsers
- Fixed-point fractional/integer part separation
Timing
The component is purely combinational with zero latency:
| Property | Latency (clock cycles) |
|---|---|
| Slice TM | 0 |
All TM phases are processed in parallel within the same clock cycle.
Typical use cases
- Extracting fractional/integer parts from fixed-point numbers
- Parsing bit fields in communication protocols
- Isolating status flags or control bits
- Building multiplexers and bit routing logic
- ADC/DAC data format conversion
Waveform example
Example with TM Factor = 4, Input = 8 bits, Start Bit = 5, Stop Bit = 2 (extracts 4 middle bits).
Note: Output is available immediately (combinational logic). Example: 0xA5 (10100101) bits [5:2] = 1001 = 0x9.