Logic NOT
Bitwise NOT operation (logical inversion). Inverts all bits of the input: each 0 becomes 1, and each 1 becomes 0. Supports configurable input width. Pure combinational logic (zero latency).
Introduction
This block performs a bitwise NOT operation (logical inversion) on the input signal. Each bit of the input is inverted: 0 becomes 1, and 1 becomes 0.
The operation is purely combinational with zero clock latency:
$$ \mathrm{OUT}(n) = \neg \mathrm{IN}(n), $$
where $\neg$ represents the logical NOT operation. The input width is configurable from 1 to any required number of bits.
Pin Description
Properties
Functional description
The component implements a bitwise NOT gate (also called inverter) in VHDL. Each bit of the input is inverted independently:
$$ y[i] = \neg x[i], $$
where:
- $x[i]$ → bit $i$ of the input
- $y[i]$ → bit $i$ of the output
- $\neg$ → logical NOT operation
The NOT gate is a fundamental building block in digital logic that performs logical negation:
| IN | OUT |
|---|---|
| 0 | 1 |
| 1 | 0 |
For multi-bit inputs, the operation is applied independently to each bit position.
Example
Given an 8-bit input 10110011:
- Output:
01001100(each bit inverted)
Mathematical background
The NOT operation is one of the three basic Boolean operations (AND, OR, NOT). It implements logical negation:
$$ \neg 0 = 1 $$ $$ \neg 1 = 0 $$
In Boolean algebra, the NOT operation has the following properties:
- Involution: $\neg(\neg x) = x$ (double negation)
- De Morgan’s laws: $\neg(x \land y) = (\neg x) \lor (\neg y)$
Timing
The component is purely combinational with zero latency:
| Property | Latency (clock cycles) |
|---|---|
| Logic NOT | 0 |
The output changes immediately (after propagation delay) when the input changes.
Typical use cases
- Signal inversion in control logic
- Implementing active-low signals
- Building blocks for more complex Boolean functions
- Bitwise complement operations
- De Morgan’s law transformations