Block Preview

Introduction

This block performs a left shift operation on standard (non-TM) data streams. Each bit of the input is shifted left by the specified Shift amount, and zeros are inserted in the vacant rightmost positions.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT}(n) = \mathrm{IN}(n) \ll S, $$

where $S$ is the Shift parameter.

Pin Description

IN Input Variable bit BIT VECTOR
Input binary data (non-TM). Width: Input Size bits
Default: Must be connected
OUT Output Variable bit BIT VECTOR
Left-shifted output (non-TM). Width depends on Output Size mode. Output is combinational (zero latency).

Properties

Property window

Input Size InputWordSize

Set the input word size in bits

Number of bits per input sample. Range: 2 – 16384.

Default: 16

Range: 2 – 16384

Shift Shift

Number of bit to be shifted

Number of bit positions to shift left. Range: 0 – 16384.

Default: 1

Range: 0 – 16384

Output Size OutputSize

Select if output should have same size of input or should be INPUT_SIZE-SHIFT

Output bit width mode:

  • SAME SIZE → Output width = Input width (MSBs truncated)
  • SHIFTED SIZE → Output width = Input width + Shift (no truncation)

Default: SAME SIZE

Options: SAME SIZE SHIFTED SIZE

Functional description

The component implements a bitwise left shift in VHDL.

The left shift operation appends $S$ zero bits to the right of the input:

$$ y = x \times 2^S $$

Output size modes

The block offers two output width configurations:

  • SAME SIZE: Output width = Input width (MSBs discarded)
  • SHIFTED SIZE: Output width = Input width + Shift (all bits preserved)

Example

Given an 8-bit input 10110011 and shift amount = 3:

  • Full result (11 bits): 10110011000
  • SAME SIZE (8 bits): 10011000 (MSBs discarded)
  • SHIFTED SIZE (11 bits): 10110011000 (all bits preserved)

Timing

The component is purely combinational with zero latency.

Typical use cases

  • Fast multiplication by powers of 2
  • Bit field manipulation and packing
  • Fixed-point rescaling