Xilinx
HLS
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Introduction

The Complex Negate block outputs the arithmetic negation of the complex input sample:

      OUT_I[n] = -IN_I[n]
    OUT_Q[n] = -IN_Q[n]

Equivalently, with X = IN_I + j*IN_Q,

      OUT = -X = X * exp(j*pi)

Negation rotates the phasor by 180 degrees (arg(OUT) = arg(X) + pi) while leaving the magnitude unchanged. Data is signed two’s complement.

Pin Description

IN_I Input InputSize bit BIT VECTOR
In-phase (I) input sample. Signed, Input Bit Width bits.
Default: Must be connected
IN_Q Input InputSize bit BIT VECTOR
Quadrature (Q) input sample. Signed, Input Bit Width bits.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset.
Default: Default Board Reset
OUT_I Output InputSize + 1 bit BIT VECTOR
In-phase (I) output = -IN_I. Signed, InputSize + 1 bits.
OUT_Q Output InputSize + 1 bit BIT VECTOR
Quadrature (Q) output = -IN_Q. Signed, InputSize + 1 bits.

Properties

Property window

Input Bit Width InputSize

Bit width of each I/Q sample (signed).

Bit width of each signed I / Q input sample. Range 4 to 32, default 16. The output width is InputSize + 1.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Output Width OutputWidth

Max = InputSize+1 (full precision, holds -(-2^(N-1))). Same as input = InputSize (no growth; SATURATED if the negated value exceeds the input range).

Default: Max (In+1)

Options: Max (In+1) Same as input

Usage

Bit widths

Data is signed two’s complement.

  • IN_I, IN_Q : signed InputSize bits.
  • OUT_I, OUT_Q : signed InputSize + 1 bits.

The output carries one extra bit because negating the most-negative value (-2^(InputSize-1)) does not fit in InputSize bits; the guard bit keeps the result exact for every input. Truncate downstream if you need to return to InputSize bits.

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one sample pair per clock.
  • 1-clock latency.
  • All data ports use the ap_none interface (no ready/valid handshake); the core is free-running (ap_ctrl_none).

Reset

RESET is the HLS synchronous reset (ap_rst).

Typical applications

  • Sign inversion of one branch of a differential / balanced datapath.
  • 180-degree phase shift of a baseband phasor.
  • Building block : A - B can be formed as A + negate(B).

Resources & Timing

  • Latency: 1 clock cycle

  • Throughput: 1 sample per clock (II=1)

No multipliers or DSPs: two negations only. Implemented with Vitis HLS. Free-running core (ap_ctrl_none), no handshake logic.