Block Preview

Introduction

This block converts serial data to parallel by shifting in bits one per clock cycle and assembling them into a parallel word. Useful for receiving serial communications.

Pin Description

SERIAL_IN Input 1 bit BIT
Serial input (1-bit). Shifts in one bit per clock cycle when CE=1.
Default: Must be connected
CE Input 1 bit BIT
Clock enable (1-bit). Must stay HIGH during deserialization.
Default: Must be connected
LE Input 1 bit BIT
CLK Input 1 bit BIT
Clock signal for shift operations.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset.
Default: Must be connected
DATA Output Variable bit BIT VECTOR
Parallel output data. Width: Parallel Width. Valid after N clock cycles.
DV Output 1 bit BIT
SERIAL_OUT Output 1 bit BIT

Properties

Property window

Bit Order BitOrder

Set the order of the serialized bit

Bit reception order: MSB FIRST or LSB FIRST.

Default: MSB FIRST

Options: MSB FIRST LSB FIRST

Latch Mode Mode

Select if latch output on latch or after the Parallel Width bits count from STREAM_START signal

Default: LATCH OUTPUT

Options: LATCH OUTPUT COUNT BITS

Parallel Width BusWidth

Set the size in bits of the output deserialized parallel word width

Parallel word width. Range: 2-65535 bits.

Default: 16

Range: 2 – 65535

Functional description

Operation sequence:

  1. Assert CE=1 to enable shifting
  2. Input bits arrive on SERIAL_IN, one per clock cycle
  3. After N clock cycles, parallel word appears on DATA

Bit order

  • MSB FIRST: First bit received becomes MSB of output word
  • LSB FIRST: First bit received becomes LSB of output word

Timing

Latency: N clock cycles (where N = Parallel Width). Shift rate: 1 bit per clock cycle.

Typical use cases

  • Serial communication receivers (SPI, UART)
  • Bit-serial data recovery
  • Data width conversion