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Introduction

ATI_LE_LINEAR implements a linear-interpolated leading-edge trigger suitable for precise time-of-arrival measurements on analog pulses.

Let

$$ \begin{aligned} V[n] &= \text{input sample at clock } n,\ \mathrm{THR} &= \text{programmable threshold}. \end{aligned} $$

A trigger is detected whenever the signal crosses the threshold from below:

$$ V[n-1] \ge \mathrm{THR} ;\land; V[n] < \mathrm{THR}, $$

where THR is the programmable Threshold input. The exact crossing point is found by linear interpolation:

$$ x = \frac{\mathrm{THR} - V[n-1]}{V[n] - V[n-1]};;,\qquad 0 \le x < 1, $$

which is internally represented on 4 fractional bits ($x_\text{fixed}= \lfloor 16,x \rfloor$).

The 48-bit output time-stamp is therefore

$$ T_\text{out}= (N_{\text{clk}}\ll4)+x_\text{fixed}, $$

offering a resolution of $T_\mathrm{s}/16$, where $T_\mathrm{s}$ is the sampling period.

Pin Description

In Input 16 bit BIT VECTOR
Sampled amplitude input. Unsigned 16-bit data representing the analog signal to be timestamped.
Threshold Input 16 bit BIT VECTOR
16-bit leading edge threshold level. The trigger fires when the input signal crosses this level. Default value: 16 (0x0010).
T0 Input 1 bit BIT
Timestamp reset. When asserted high for one clock the internal coarse counter is cleared to zero; useful for run-start alignment.
CLK Input 1 bit BIT
System clock driving the sampling of In and all internal logic. The sampling period $T_\mathrm{s}=1/f_\mathrm{CLK}$ defines the coarse time quantum of the output timestamp.
Default: Default Board Clock
RESET Input 1 bit BIT
Global synchronous reset. Clears pipeline registers, FSM state and forces TRIGGER = 0, DV = 0.
Default: Default Board Reset
TIMESTAMP Output 48 bit BIT VECTOR
48-bit time-tag = {counter[43:0], fraction[3:0]}. Valid only when DV = 1 (one clock cycle).
TRIGGER Output 1 bit BIT
One-clock event pulse indicating detection of a valid threshold crossing. Fired when the signal overcomes the Threshold.
DV Output 1 bit BIT
Data Valid strobe. High for exactly one clock cycle while TIMESTAMP holds a stable event value.

Usage

Functional overview

ATI_LE_LINEAR is a three-stage finite-state machine:

State Action
IDLE Wait for leading edge threshold crossing condition.
MEAS1 Store $(V[n-1], V[n])$ and raise TRIGGER for one cycle.
OUTPUT Compute fractional delay, deliver 48-bit TIMESTAMP, assert DV, return to IDLE.

Internally a 44-bit free-running counter timestamp_counter (incremented every clock) provides the coarse time base. On each event the counter is concatenated with the 4-bit interpolation result to form the fine-time tag.

Mathematical background

The trigger detects when the input signal crosses a fixed threshold level. This leading-edge approach is simple and effective for signals with consistent rise times.

To achieve sub-sample resolution, the discrete points $(n-1, V[n-1])$ and $(n, V[n])$ are linearly interpolated to find the exact threshold crossing; because the computation is purely arithmetic it synthesises efficiently in FPGA fabric (18-bit adders/dividers).

Timestamp format

The output timestamp is composed of:

  • TCOARSE (bits 47:4): 44-bit coarse timestamp from the free-running counter
  • TFINE (bits 3:0): 4-bit sub-sample interpolation result

Total resolution: $T_\mathrm{s}/16$ where $T_\mathrm{s}$ is the sampling period.

Practical use-case

Typical applications include:

  • Scintillator detectors with PMT or SiPM readout.
  • Nuclear physics time-of-flight measurements.
  • Radiation detection systems requiring precise timing.
  • Any application where signals have consistent shapes.

Timing

  • Latency (CLK domains): • 1 cycle from threshold crossing to TRIGGER assertion • 2 cycles from threshold crossing to TIMESTAMP / DV

  • Throughput: one sample per clock. Dead time is 2 cycles after a trigger event.

Example

The following table shows example data with threshold interpolation results:

Threshold Correction Time
1194 0 464
1195 0 464
1196 -0.9375 465
1220 -0.75 468
1260 -0.375 474
1300 0 480

Leading Edge Interpolation Example