Xilinx
HLS
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Introduction

The QDC/PSD HLS block implements digital charge integration (QDC) with optional Pulse Shape Discrimination (PSD) for particle identification.

PSD is used to distinguish different particle types (e.g., neutrons vs. gammas) based on their scintillation pulse shape. Different particles produce different light decay time constants in scintillators, allowing discrimination by comparing charge integrated over different time windows.

The block provides:

  • Qlong: Total charge integrated over the long gate
  • Qshort: Charge integrated over the short gate (fast component)
  • PSD: Ratio of Qshort/Qlong or Qlong/Qshort (selectable)

The core uses Xilinx HLS for efficient FPGA implementation with II=1 throughput.

Pin Description

AN In Input 16 bit BIT VECTOR
16-bit analog input signal from ADC. Connected to the detector output (typically through preamplifier or direct PMT/SiPM).
Default: Must be connected
TRIGGER IN Input 1 bit BIT
Trigger input pulse. Starts the integration process. HIGH for one clock cycle at the pulse detection time.
Default: Must be connected
BASELINE IN Input 16 bit BIT VECTOR
16-bit baseline value to subtract from input samples. Connect to a baseline restorer output for DC offset removal. Set to 0 if no baseline subtraction is needed.
PRE INT Input 16 bit BIT VECTOR
16-bit pre-integration time in clock cycles. Number of samples to integrate BEFORE the trigger. Captures the rising edge of the pulse. Typical values: 5-50 samples.
QLONG TIME Input 16 bit BIT VECTOR
16-bit long integration gate duration in clock cycles. Total integration time after trigger for Qlong. Should capture the full pulse including the slow decay component. Typical values: 200-2000 samples depending on scintillator decay time.
QSHORT TIME Input 16 bit BIT VECTOR
16-bit short integration gate duration in clock cycles. Integration time after trigger for Qshort. Should capture mainly the fast component of the pulse. Typical values: 20-100 samples.
QSHORT DELAY Input 16 bit BIT VECTOR
Start of the QSHORT gate, measured from the trigger, in ADC samples (the core runs one sample per clock). On a trigger the block loads this value into a wait counter and holds the short gate LOW while it counts down; the gate then opens for QSHORT TIME samples. So the short window is [trigger + QSHORT DELAY, trigger + QSHORT DELAY + QSHORT TIME), while QLONG starts at the trigger itself. The counter is reloaded on the retrigger / pile-up path as well, so a rejected event does not shift the short gate of the next one.
POST INIB Input 16 bit BIT VECTOR
16-bit post-integration inhibit time in clock cycles. Additional dead time after QLONG_TIME ends. Events during this window cause single-event rejection (DREJ). Prevents pile-up from affecting subsequent measurements.
GAIN Input 16 bit BIT VECTOR
16-bit gain factor for 16-bit output scaling. Represents a value between 0 (0x0000) and 1 (0xFFFF). Applied to QLONG_32 and QSHORT_32 to generate 16-bit outputs. Adjust to fit the charge range in 16 bits.
TIMETAG Input 64 bit BIT VECTOR
64-bit timestamp input. Captured at trigger time and output on TIMESTAMP.
RST_STAT Input 1 bit BIT
Reset statistics signal. Clears rejection counters REJ_CNT and DREJ_CNT when asserted.
CLK Input 1 bit BIT
System clock input. All operations are synchronous to the rising edge.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset. Clears all internal state and accumulators.
Default: Default Board Reset
DATA_OUT Output 16 bit BIT VECTOR
16-bit delayed input signal output. Input signal delayed by the IP pipeline for alignment.
DATA_VALID Output 1 bit BIT
Data valid strobe. HIGH for one clock cycle when QLONG, QSHORT, and PSD outputs are valid.
QLONG_32 Output 32 bit BIT VECTOR
32-bit long integration result (full resolution). Raw charge sum without gain applied.
QSHORT_32 Output 32 bit BIT VECTOR
32-bit short integration result (full resolution). Raw charge sum without gain applied.
QLONG_16 Output 16 bit BIT VECTOR
16-bit long integration result. Qlong_32 scaled by GAIN for reduced data width.
QSHORT_16 Output 16 bit BIT VECTOR
16-bit short integration result. Qshort_32 scaled by GAIN for reduced data width.
QLONG_GATE Output 1 bit BIT
Qlong integration gate signal. HIGH during the long integration window.
QSHORT_GATE Output 1 bit BIT
Qshort integration gate signal. HIGH during the short integration window.
PSD Output 32 bit BIT VECTOR
32-bit PSD ratio output. Fixed-point ratio (Qlong/Qshort or Qshort/Qlong based on PSD Mode). Maximum value (2^32) when ratio equals 1.
TIMESTAMP Output 64 bit BIT VECTOR
64-bit timestamp output. Captured TIMETAG value at trigger time.
INIB Output 1 bit BIT
Inhibit signal. HIGH when integration is in progress and new triggers are blocked.
REJ Output 1 bit BIT
Rejection flag (pulse). HIGH when a pile-up during QLONG window caused both events to be rejected.
DREJ Output 1 bit BIT
Double rejection flag (pulse). HIGH when a pile-up during POST_INIB caused the second event to be rejected.
REJ_CNT Output 32 bit BIT VECTOR
32-bit rejection counter. Counts events rejected due to pile-up during QLONG window. Reset by RST_STAT.
DREJ_CNT Output 32 bit BIT VECTOR
32-bit double rejection counter. Counts events rejected due to pile-up during POST_INIB. Reset by RST_STAT.

Properties

Property window

Enable PSD use_psd

Default: False

PSD Mode psd_mode

Select PSD calculation mode

Default: Qlong/Qshort

Options: Qlong/Qshort Qshort/Qlong

EnablePSD EnablePSD
Enable PSD calculation. When disabled, only QDC (charge integration) is performed. Available values: True, False, default False.
PSDMode PSDMode

PSD calculation mode.

  • Qlong/Qshort: PSD = (Qlong / Qshort) * 2^32
  • Qshort/Qlong: PSD = (Qshort / Qlong) * 2^32 Available values: Qlong/Qshort, Qshort/Qlong, default Qlong/Qshort.

Usage

PSD Principle

PSD diagram

The figure illustrates the pulse shape discrimination principle:

  • Qlong integrates the full pulse (PRE_INT to QLONG_TIME after trigger)
  • Qshort integrates only the fast component (PRE_INT to QSHORT_TIME after trigger)
  • The ratio between these charges discriminates particle types

PSD Calculation Modes

The PSD value can be calculated using two formulas, selectable via the PSD Mode property:

Mode 1: Qlong/Qshort (default)

$$ \text{PSD} = \frac{Q_{\text{long}}}{Q_{\text{short}}} \times 2^{32} $$

Mode 2: Qshort/Qlong

$$ \text{PSD} = \frac{Q_{\text{short}}}{Q_{\text{long}}} \times 2^{32} $$

The choice depends on the application:

  • Qlong/Qshort: Larger values for particles with slower decay (e.g., neutrons in organic scintillators)
  • Qshort/Qlong: Complementary ratio, may be preferred for some analysis methods

Integration Timing

The charge integration windows are defined as:

  Trigger
   |
   v
|--PRE_INT--|------------------QLONG_TIME-----------------|--POST_INIB--|
            |--------QSHORT_TIME--------|
            ^                           ^                              ^
            |                           |                              |
       Integration                 Qshort ends                   Ready for
         starts                                                  next event
  • PRE_INT: Samples to include before the trigger (captures rising edge)
  • QLONG_TIME: Duration of long integration gate after trigger
  • QSHORT_TIME: Duration of short integration gate after trigger
  • POST_INIB: Additional dead time after Qlong for pile-up rejection

Pile-Up Rejection

The block implements non-paralyzable pile-up rejection:

Event Timing Behavior
Trigger during QLONG window Both events rejected (REJ flag)
Trigger during POST_INIB Only second event rejected (DREJ flag)
Trigger after POST_INIB Both events accepted normally

Rejection counters (REJ_CNT, DREJ_CNT) track discarded events for rate analysis.

Output Formats

The block provides charge values in two formats:

Output Bits Gain Applied Use Case
QLONG_32 / QSHORT_32 32 No Full resolution for analysis
QLONG_16 / QSHORT_16 16 Yes Reduced data for histogramming

The GAIN parameter scales the 32-bit values to fit in 16 bits:

$$ Q_{16} = \frac{Q_{32} \times \text{GAIN}}{65536} $$

Baseline Subtraction

The BASELINE IN input allows real-time baseline subtraction:

$$ Q = \sum_{i=0}^{N} (x[i] - \text{baseline}) $$

Connect a baseline restorer block output to remove DC offset and improve energy resolution.

Timing and Latency

  • Processing latency: 13 clock cycles
  • Throughput: 1 sample per clock cycle (II=1)

Typical Applications

  • Neutron/gamma discrimination with organic scintillators (EJ-301, BC-501A)
  • Alpha/beta discrimination in liquid scintillators
  • Phoswich detector readout
  • PET timing measurements
  • General charge integration for PMT/SiPM signals