Xilinx
TM
HLS
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Introduction

Per lane, over each block of N samples:

$$ \mathrm{SKEW}_i = \frac{m_3}{m_2^{3/2}} = \frac{N^2 S_3 - 3N S_1 S_2 + 2S_1^3}{\bigl(N S_2 - S_1^2\bigr)^{3/2}} \qquad (S_1, S_2, S_3\ \text{of lane } i) $$

This is the time multiplexed (TM) twin of the scalar Block Skewness block: TM Factor independent channels packed on one wide bus, each computing the skewness of its own block of N consecutive samples. Nothing is shared between the channels except the frame.

Per lane it is dimensionless and gain independent, EXACTLY zero for a symmetric block (the identity is exact integer arithmetic, so a symmetric lane reads 0, not “nearly zero”) - which is what makes a lane usable as a pulse-on-pedestal trigger.

The TM contract

  • IN is TM Factor lanes of input width bits each, lane 0 in the LOW bits (lane 0 is the oldest sample of the clock) - the same packing as every other TM block in the toolchain. Each lane is an independent channel: its own S1 / S2 / S3 accumulators, its own result.
  • ONE shared EXP pin, ONE IN_DV, one frame: all lanes start and end their blocks on the same accepted clocks. BUSY, INTEGRATING and SAMPLE_COUNT therefore stay scalar - SAMPLE_COUNT counts per-lane samples, which are identical in every lane by construction.
  • Accumulation runs at II=1 on the packed bus, one accumulator set per lane. TM Factor times the accumulator registers is the unavoidable cost of TM state - plus TWO real multipliers per lane (xx and (xx)*x) in the accumulation path.
  • The serial post-processing is ONE shared engine set serving the lanes one after the other: the three shift-add products, the digit-recurrence root, the D*root product and the restoring division are each ONE stage, iterating lane by lane - not TM Factor of each. That is what keeps the tail resources of the SCALAR block, at the cost of tail latency x TM Factor.
  • ONE OUT_DV per block, after the LAST lane’s tail completes. All output lanes are staged as each lane finishes and committed together on the OUT_DV clock, so every packed output moves on that clock and no other.

N is a runtime input: the block size is $N = 2^{\mathrm{EXP}}$, EXP clamped to Max Block Exponent and latched on the first accepted sample of a block, so a change takes effect on the NEXT block - for every lane at once. Because N is a power of two, every N scaling in the identity is an exact shift and the N^3 factors cancel exactly between numerator and denominator - per lane.

When to use this instead of TM Factor scalar blocks

One TM block and TM Factor scalar blocks compute the same numbers. The TM block pays the per-lane accumulators (unavoidable either way) but shares ONE frame, ONE control FSM and ONE serial tail across all lanes - the more expensive the scalar tail, the more it saves, and this one’s tail is three products, a root and a division. The price is tail latency (TM Factor times the scalar tail) and the coupling of the frame: all lanes must share the same block length and the same sample cadence. Channels that need different block sizes need scalar blocks.

Pin Description

IN Input (IN_BitsInt + IN_BitsFract) * TMFactor bit TM
Packed TM sample bus: TM Factor lanes of input width bits, lane 0 in the LOW bits. Each lane is an independent channel, accumulated (S1, S2, S3) only on the clocks where IN_DV is high.
Default: Must be connected
IN_DV Input 1 bit BIT
Per-sample qualifier for ALL lanes at once, active high, the only qualifier this block has (no CE pin, by family rule - gate this instead). Unconnected defaults to ‘1’.
EXP Input 6 bit BIT VECTOR
Block size exponent, shared by every lane: each lane’s block is 2^EXP samples of THAT lane. 6 bits, clamped to Max Block Exponent, latched on the first accepted sample of a block. Unconnected defaults to 10 (N = 1024) - note that the DEFAULT FORMATS need EXP >= 11 at TM 4 (see “Timing”).
SKEWNESS Output (SKEW_BitsInt + SKEW_BitsFract) * TMFactor bit TM
Packed per-lane skewnesses, lane 0 in the LOW bits. Per lane: 0 for a symmetric block (exactly), positive when the long tail points up, negative when it points down.
OUT_DV Output 1 bit BIT
ONE one-clock pulse per block, L clocks after the N-th sample was accepted - after the LAST lane’s tail completed. Every packed output updates on this clock and on no other.
CLK 1 bit
Clock.
RESET 1 bit
Synchronous reset: clears every lane, the shared frame and the tail.
BUSY 1 bit
Shared by all lanes: high from the first sample of a block until the LAST lane’s result is out (it covers the whole lane-multiplexed tail); its last high clock is the OUT_DV pulse. Present only when Enable BUSY = YES.
INTEGRATING 1 bit
Shared by all lanes: high only while the block is accumulating. The clock it falls on is the one where SAMPLE_COUNT always reads N. Present only when Enable INTEGRATING = YES.
SAMPLE_COUNT 1 bit
Shared by all lanes (they advance in lockstep): samples accumulated so far in the current block, 1 after the first, N after the N-th. NOT cleared at the block end; on a continuous stream it has already restarted by OUT_DV, so latch it when INTEGRATING falls. 32 bits. Present only when Enable SAMPLE_COUNT = YES.

Properties

Property window

IN Integer Bits IN_BitsInt

Number of INTEGER bits of the input sample (per lane) (the sign, when present, uses one of them).

Integer bits of ONE LANE of the input (the sign, when present, uses one of them). 1..64. Default 16.

Default: 16

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

IN Fractional Bits IN_BitsFract

Number of FRACTIONAL bits of the input sample (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.

Fractional bits of one lane of the input. 0..64, total lane width 2..64 bits. Default 0. They cancel exactly - the skewness is dimensionless.

Default: 0

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

IN Sign IN_Sign

Select whether the input sample (per lane) is signed (two’s complement) or unsigned.

SIGNED (two’s complement) or UNSIGNED lanes. Default SIGNED. Applies to every lane.

Default: SIGNED

Options: UNSIGNED SIGNED

TM Factor TMFactor

Number of INDEPENDENT time-multiplexed channels packed on the IN bus and on every result bus. Lane 0 occupies the LOW bits (lane 0 = the oldest sample of the clock), the same packing as every other TM block. All lanes share one EXP / IN_DV / frame; each lane gets its own accumulators, but the serial post-processing is ONE engine serving the lanes one after the other, so the tail latency (and the minimum usable EXP) grows with this factor.

Number of independent channels packed on the buses, 2..16. Default 4. Multiplies the IN width, every packed output width AND the serial tail length (the shared tail serves the lanes one after the other), so it also raises the minimum usable EXP.

Default: 4

Options: 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Max Block Exponent MaxBlockExponent

Largest block-size exponent the accumulators are sized for: the block can be up to 2^MaxBlockExponent samples long. The EXP input is clamped to this value at run time. Raising it widens the internal accumulators, and ON THE BLOCKS WHOSE SERIAL ENGINES ARE SIZED FROM THOSE ACCUMULATORS (Coefficient of Variation, SNR, Skewness, Kurtosis, Correlation, Autocorrelation, Linear Regression) it also LENGTHENS THE SERIAL TAIL – even when the runtime EXP is small. Keep it at the largest block you actually use. The default of 20 covers blocks of up to 1048576 samples.

Largest block-size exponent the per-lane accumulators are sized for; the EXP input is clamped to it at run time. Raising it widens every lane’s S1 / S2 / S3 accumulators AND lengthens the shared products, root and divider. 1..31, default 20.

Default: 20

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SKEW Integer Bits SKEW_BitsInt

Number of INTEGER bits of the SKEWNESS output (per lane) (the sign, when present, uses one of them).

Integer bits of ONE LANE of the SKEWNESS output. 1..64, default 6.

Default: 6

Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SKEW Fractional Bits SKEW_BitsFract

Number of FRACTIONAL bits of the SKEWNESS output (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.

Fractional bits of one lane. 0..64, default 10. Each one also lengthens the shared divider by one clock per lane.

Default: 10

Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SKEW Sign SKEW_Sign

Select whether the SKEWNESS output (per lane) is signed (two’s complement) or unsigned.

SIGNED or UNSIGNED lanes. Default SIGNED - the sign IS the asymmetry direction.

Default: SIGNED

Options: UNSIGNED SIGNED

Enable BUSY EnableBusy

YES: the BUSY (high from the first sample of a block until its result is out – it COVERS THE SERIAL TAIL, and its last high clock IS the OUT_DV pulse) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.

YES: the shared BUSY pin exists. Default NO.

Default: NO

Options: NO YES

Enable INTEGRATING EnableIntegrating

YES: the INTEGRATING (high only while the block is ACCUMULATING; it drops as soon as the N-th sample has been taken and the tail starts, so BUSY-and-not-INTEGRATING means ‘computing’) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.

YES: the shared INTEGRATING pin exists. Default NO.

Default: NO

Options: NO YES

Enable SAMPLE_COUNT EnableSampleCount

YES: the SAMPLE_COUNT (32 bit, how many samples have been accumulated so far in the current block: 1 after the first, N after the N-th. It is NOT cleared at the block end – it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail, so at OUT_DV it reads how far into the next block the input has already got, NOT N. To capture the length of the block being presented, latch SAMPLE_COUNT on the clock INTEGRATING falls – that one always reads N) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.

YES: the shared 32 bit SAMPLE_COUNT pin exists. Default NO.

Default: NO

Options: NO YES

Rounding Rounding

ROUND: round to nearest when a result has to be requantised into a coarser output format. TRUNCATE: drop the bits (cheaper, adds a negative bias).

ROUND / TRUNCATE at each lane’s final requantisation. Effectively a NO-OP on this block: the numerator is pre-shifted so each lane’s quotient already carries exactly the output resolution and nothing is left to shift. Saturation still applies. Default ROUND.

Default: ROUND

Options: TRUNCATE ROUND

Saturation EnableSaturation

YES: clip to the largest representable value of each output format (symmetric for signed formats). NO: wrap around.

YES: clip each lane to its output format (symmetric for signed). NO: wrap. Default YES.

Default: YES

Options: NO YES

Accuracy, per lane

Each lane carries the scalar twin’s bound: everything up to the root is exact integer arithmetic, the root is up to 1 ulp low at 2^-SQG of an output LSB, and the quotient is floored - it already comes out at exactly the output resolution, so nothing is shifted or re-rounded afterwards. Each lane’s SKEWNESS is within 1 LSB, plus the scalar twin’s small per-block, value-dependent allowance that propagates the truncated root through the division (about 2*|skew| / root - a fraction of an LSB for any block whose variance numerator is of realistic size); this is NOT a flat bound, and the harness enforces it per block, per lane. Symmetric and constant lane blocks are checked at tolerance 0: they must read EXACTLY 0. Each lane is bit-identical to the scalar twin run on the same lane stream.

Because each lane’s quotient already carries the output resolution, the Rounding property is effectively a NO-OP on this block (saturation still applies).

Timing: the TM latency contract

OUT_DV pulses ONCE per block, L clocks after the clock on which the N-th sample was accepted, where

$$ L = 1 + \mathrm{TM},\bigl(3(\mathrm{IN_SW} + \mathrm{EXP}) + 2,\mathrm{RTW} + \mathrm{CNUMW} + 3\bigr) $$

(BSKT_TAIL in the core). Note the per-lane cost is L_scalar - 2, one clock LESS than the family’s usual $L_{tm}(e) = \mathrm{TM},(L_{scalar}(e)-1)+1$ rule: the scalar FSM’s separate radicand-load state is MERGED into the variance state (D is computed and the radicand loaded on the same clock), and lane ln+1’s engines are reloaded during lane ln’s FIN clock, so there is no separate load state anywhere. Pure data movement - the values are bit-identical; only the timing differs. The tail DEPENDS ON THE RUNTIME EXPONENT through the three products. At the defaults (16 bit signed input, Q6.10 SKEWNESS, Max Block Exponent 20, TM 4, EXP 10) RTW = 40 and CNUMW = 122, so L = 1 + 4*283 = 1133 clocks - which does NOT fit a 2^10 block: at those defaults the minimum usable EXP is 11.

The family drop rule applies with the TM tail: the tail of one block must finish before the NEXT block completes, $2^{{\mathrm{{EXP}}}} \ge L$, or the completing block’s result is silently DROPPED (no OUT_DV, accumulators unaffected, no error pin). The TM tail makes the minimum usable EXP larger than the scalar twin’s - the compiler prints both the worst-case tail and the minimum EXP in the compilation log, and the property window refuses a configuration whose minimum exceeds Max Block Exponent.

Knowing where the block is: BUSY, INTEGRATING and SAMPLE_COUNT

Identical to the scalar family, and SHARED by all lanes: INTEGRATING is high exactly while the block is accumulating (it dips one clock per block boundary on a continuous stream), BUSY also covers the (TM-long) tail and its last high clock IS the OUT_DV pulse, SAMPLE_COUNT reads 1 after the first accepted sample and N after the N-th.

SAMPLE_COUNT is NOT cleared at the block end - it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail (which on a TM block is TM Factor times longer), so at OUT_DV it reads how far into the next block the input has got, NOT N. The clock that always reads N is the one INTEGRATING falls on - latch it there.

Verification

The core is regression tested by a host-side csim harness (tb/block-ops-tm/run_tb_tm.ps1) with per-lane goldens computed by gen_golden_tm.py in exact rational arithmetic ON EACH LANE’S STREAM ALONE (lanes deliberately carry different signals - the generator refuses identical lanes), from the TEXTBOOK central-moment definition, never from the raw-power-sum identity the core uses - so the algebra is checked against an independent derivation. Plus the strongest available lane-independence check: after every run, the SCALAR twin is replayed on each lane’s stream by itself and lane k of every TM result must match it BIT FOR BIT. The status waveform is checked clock by clock, every packed output is checked to move only on OUT_DV, and the TM-specific mutant classes (shared accumulator, lane swaps, wrong-lane tail reads, early commit, drop rule) are killed. What no host harness can prove - that Vitis accepts and schedules the core at II=1 - is stated in AGENT/block_ops.log, not silently implied. Note also that the DEFAULT wide formats are beyond the host stub’s 127-bit ceiling (3*(IN_SW + Max Block Exponent) + guard bits): they are exercised only by csynth, and the harness scenarios use narrower inputs. Said openly rather than implied away.