Block Preview

Introduction

This block performs a bitwise OR operation on multiple input signals (configurable from 2 to 1024 inputs). All inputs must have the same bit width.

The output is 1 (HIGH or True) if at least one corresponding input bit is 1. The output is 0 (LOW or False) only when all input bits are 0.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT} = \mathrm{IN}_0 \lor \mathrm{IN}_1 \lor \ldots \lor \mathrm{IN}_N, $$

where $\lor$ represents the logical OR operation and $N$ is the number of inputs.

Pin Description

IN_0 Input -1 bit BIT VECTOR
IN_1 Input -1 bit BIT VECTOR
OUT Output Variable bit BIT VECTOR
OR result output, same width as inputs. Each output bit is the logical OR of all corresponding input bits. Output is combinational (zero latency).
IN0, IN1, ..., IN(N-1) Variable bit
Input binary data signals. Number of inputs: Configurable from 2 to 1024 (set at creation time). Width: All inputs must have the same bit width (configurable). Each input contributes to the OR operation at each bit position.
Default: Must be connected

Properties

Property window

Number of inputs InputCount

Set the number of input to the virtual block

Number of input signals to the OR gate. Range: 2 to 1024. This property is set during block creation and defines how many input pins the component will have.

Default: 2

InputWordSize InputWordSize
Number of bits for each input and the output signal. All inputs and the output share the same bit width. The OR operation is applied independently to each bit position.

Functional description

The component implements a multi-input bitwise OR gate in VHDL. Each bit position of the output is the OR of all corresponding input bits:

$$ y[i] = x_0[i] \lor x_1[i] \lor \ldots \lor x_N[i], $$

where:

  • $x_k[i]$ → bit $i$ of input $k$
  • $y[i]$ → bit $i$ of the output
  • $\lor$ → logical OR operation

The OR gate is one of the fundamental building blocks in digital logic. It implements logical disjunction:

IN0 IN1 OUT
0 0 0
0 1 1
1 0 1
1 1 1

For multi-bit inputs, the operation is applied independently to each bit position. In another sense, the logic OR gate effectively finds the maximum between the input binary digits.

Example

Given two 8-bit inputs:

  • IN0: 10110011
  • IN1: 01010101

Output: 11110111 (bitwise OR of all inputs)

Mathematical background

The OR operation is one of the three basic Boolean operations (AND, OR, NOT). It implements logical disjunction:

$$ 0 \lor 0 = 0 $$ $$ 0 \lor 1 = 1 $$ $$ 1 \lor 0 = 1 $$ $$ 1 \lor 1 = 1 $$

In Boolean algebra, the OR operation has the following properties:

  • Commutativity: $x \lor y = y \lor x$
  • Associativity: $(x \lor y) \lor z = x \lor (y \lor z)$
  • Identity element: $x \lor 0 = x$
  • Annihilator: $x \lor 1 = 1$

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Logic OR 0

The output changes immediately (after propagation delay) when any input changes.

Typical use cases

  • Combining multiple enable signals
  • Error flag aggregation
  • Building blocks for more complex Boolean functions
  • Priority encoding logic
  • Interrupt signal collection