Block Preview

Introduction

This block performs a bitwise XOR (exclusive OR) operation on multiple input signals (configurable from 2 to 1024 inputs). All inputs must have the same bit width.

The output is 1 (HIGH or True) if the number of 1 input bits is odd, otherwise the output is 0 (LOW or False). XOR can be viewed as addition modulo 2 and is fundamental in binary adders and parity checkers.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT} = \mathrm{IN}_0 \oplus \mathrm{IN}_1 \oplus \ldots \oplus \mathrm{IN}_N, $$

where $\oplus$ represents the logical XOR operation and $N$ is the number of inputs.

Pin Description

IN_0 Input -1 bit BIT VECTOR
IN_1 Input -1 bit BIT VECTOR
OUT Output Variable bit BIT VECTOR
XOR result output, same width as inputs. Each output bit is the logical XOR of all corresponding input bits. Output is combinational (zero latency). Output is 1 when an odd number of corresponding input bits are 1.
IN0, IN1, ..., IN(N-1) Variable bit
Input binary data signals. Number of inputs: Configurable from 2 to 1024 (set at creation time). Width: All inputs must have the same bit width (configurable). Each input contributes to the XOR operation at each bit position.
Default: Must be connected

Properties

Property window

Number of inputs InputCount

Set the number of input to the virtual block

Number of input signals to the XOR gate. Range: 2 to 1024. This property is set during block creation and defines how many input pins the component will have.

Default: 2

InputWordSize InputWordSize
Number of bits for each input and the output signal. All inputs and the output share the same bit width. The XOR operation is applied independently to each bit position.

Functional description

The component implements a multi-input bitwise XOR gate in VHDL. Each bit position of the output is the XOR of all corresponding input bits:

$$ y[i] = x_0[i] \oplus x_1[i] \oplus \ldots \oplus x_N[i], $$

where:

  • $x_k[i]$ → bit $i$ of input $k$
  • $y[i]$ → bit $i$ of the output
  • $\oplus$ → logical XOR operation

The XOR gate is an exclusive OR gate. It implements logical exclusive disjunction:

IN0 IN1 OUT
0 0 0
0 1 1
1 0 1
1 1 0

For multi-bit inputs, the operation is applied independently to each bit position. The XOR gate outputs 1 when an odd number of inputs are 1, making it useful for parity generation and checking.

Example

Given two 8-bit inputs:

  • IN0: 10110011
  • IN1: 01010101

Output: 11100110 (bitwise XOR of all inputs)

Mathematical background

The XOR operation is one of the fundamental Boolean operations. It implements exclusive disjunction and addition modulo 2:

$$ 0 \oplus 0 = 0 $$ $$ 0 \oplus 1 = 1 $$ $$ 1 \oplus 0 = 1 $$ $$ 1 \oplus 1 = 0 $$

In Boolean algebra, the XOR operation has the following properties:

  • Commutativity: $x \oplus y = y \oplus x$
  • Associativity: $(x \oplus y) \oplus z = x \oplus (y \oplus z)$
  • Identity element: $x \oplus 0 = x$
  • Self-inverse: $x \oplus x = 0$
  • Involution: $(x \oplus y) \oplus y = x$

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Logic XOR 0

The output changes immediately (after propagation delay) when any input changes.

Typical use cases

  • Binary addition (half-adder and full-adder circuits)
  • Parity generation and checking
  • Error detection codes
  • Data encryption and scrambling
  • Difference detection between signals
  • Toggle operations