Xilinx
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Introduction

The block computes the exponential function of IEEE-754 floating-point inputs. On every rising edge of CLK, if CE = 1, the exponential unit computes

$$ \mathrm{F}(n) = e^{\mathrm{A}(n)}, $$

where input A and output F follow IEEE-754 single or double precision format, and $e \approx 2.71828$ is Euler’s number.

The exponential is implemented with the Xilinx floating_point IP core configured for Exponential operation using table-based polynomial approximation with blocking flow control, fixed 21-cycle latency, and configurable DSP and BRAM usage.

Pin Description

A Input Variable bit BIT VECTOR
Floating-point input value (IEEE-754), the exponent. Width: 32 bits (Single) or 64 bits (Double). Typical range: -87 to +88 (Single) or -708 to +709 (Double) to avoid overflow/underflow. Accepted when CE = 1 and READY_OUT = 1.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable (tvalid), active high. When CE = 1, input A is accepted and exponential computation begins. Can be tied to ‘1’ for continuous operation.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal (tready input), active high. Indicates if downstream logic can accept new data. Can be tied to ‘1’ if backpressure is not needed.
CLK Input 1 bit BIT
Global clock. Every rising edge triggers pipeline advancement. Connected to system acquisition clock.
Default: Default Board Clock
F Output 32 bit BIT VECTOR
Floating-point exponential output (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Valid when DV = 1. Result = e^A.
DV Output 1 bit BIT
Data Valid output (tvalid), active high. Indicates when output F contains a valid exponential result. Asserts 21 clock cycles after corresponding CE = 1.
READY_OUT Output 1 bit BIT
Upstream ready signal (tready output), active high. Indicates this block can accept new input data. Used for flow control in streaming pipelines.

Properties

Property window

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Floating-point precision for both input and output:

  • Single → 32-bit (8-bit exponent, 24-bit mantissa including implicit bit)
  • Double → 64-bit (11-bit exponent, 53-bit mantissa including implicit bit)

The operation preserves the precision format end-to-end.

Default: Single

Options: Single Double

DSP Usage DSPUsage

DSP Usage. Single precision: No [0], Medium [1], Full[2], Max[7]. Double precision: No[0], Medium [15], Full[26]

DSP primitive allocation for polynomial evaluation:

  • No_Usage → LUT-only (0 DSPs, lower speed)
  • Medium_Usage → Partial DSP (1/15 DSPs for Single/Double)
  • Full_Usage → Full DSP optimization (2/26 DSPs, recommended, higher speed)

Full usage provides best timing performance.

Default: Full_Usage

Options: No_Usage Medium_Usage Full_Usage

RAM Usage RAMUsage

Use LUT or BRAM in FPGA

Memory resource for lookup tables:

  • No_Usage → Distributed RAM / LUTs (more LUT usage)
  • Full_Usage → Block RAM (BRAM, saves LUTs, recommended)

BRAM usage is recommended to reduce LUT pressure.

Default: Full_Usage

Options: No_Usage Full_Usage

Functional description

The component computes the exponential function:

$$ F = e^A = \exp(A) $$

The implementation uses range reduction combined with table lookup and polynomial approximation:

$$ e^x = e^{n \ln 2 + r} = 2^n \times e^r $$

where $r \in [0, \ln 2)$ is computed via table lookup and polynomial evaluation.

Special cases

IEEE-754 special value handling:

  • exp(0) = 1
  • exp(-Inf) = +0
  • exp(+Inf) = +Inf
  • exp(x) = +Inf for large x (overflow)
  • exp(x) = +0 for large negative x (underflow)
  • exp(NaN) = NaN (NaN propagation)

Resource Usage

Two independent resource controls:

DSP Usage (polynomial evaluation):

Single precision:

  • No_Usage → 0 DSPs (LUT-based)
  • Medium_Usage → 1 DSP
  • Full_Usage → 2 DSPs (higher speed)

Double precision:

  • No_Usage → 0 DSPs (LUT-based)
  • Medium_Usage → 15 DSPs
  • Full_Usage → 26 DSPs (higher speed)

RAM Usage (lookup tables):

  • No_Usage → Distributed RAM / LUTs
  • Full_Usage → Block RAM (BRAM), saves LUTs

Recommended: Full_Usage for both DSP and RAM for optimal speed and LUT efficiency.

Timing

The IP has a fixed 21-cycle pipeline latency:

Clock cycle Event
0 Input A presented with CE = 1
21 Output F valid with DV = 1

The READY_IN/READY_OUT handshake signals enable backpressure control for streaming applications.

Typical use cases

  • Activation functions in neural networks (sigmoid, softmax)
  • Probability density functions (Gaussian, Poisson)
  • Signal decay/growth modeling
  • Time-domain filter responses