Xilinx
TM
Block Preview

Introduction

This block converts IEEE 754 floating-point values to fixed-point representation using the Xilinx Floating Point IP core. The component supports Time Multiplexing (TM): multiple parallel conversion units (phases) share the same clock cycle, enabling high sample rates with predictable latency.

On every rising edge of CLK, if CE = 1 and READY_IN = 1, the converter performs

$$ \mathrm{A}(n) = \text{fixed}\bigl(\mathrm{F}(n)\bigr), $$

where $\mathrm{F}$ is the IEEE 754 floating-point input and $\mathrm{A}$ is the fixed-point output with configurable integer and fractional bit widths. The TM Factor property determines how many parallel instances are instantiated.

Pin Description

F Input Variable bit TM

Floating-point input data, always TM. Width: (Exponent + Mantissa) × TMFactor

  • Single: 32 bits/phase → total 32×TMFactor
  • Double: 64 bits/phase → total 64×TMFactor IEEE 754 format input for conversion to fixed-point.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable / Input Valid, active high. When CE = 0 the converter pipeline is stalled. Maps to s_axis_a_tvalid in the AXI Stream interface.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal, active high. Indicates that downstream logic can accept new data. Maps to m_axis_result_tready. Default: ‘1’ if not connected.
CLK Input 1 bit BIT
Global clock. Every rising edge triggers conversion in all TM phases and advances pipeline registers.
Default: Default Board Clock
A Output 32 bit TM
Fixed-point output, always TM. Width: (IntLength + FractLength) × TMFactor Each phase produces a fixed-point value with the configured bit width. Valid after 7 clock cycles from input.
DV Output 1 bit BIT
Data Valid output, active high. Asserted when all TM phases have valid output data. Maps to AND of all m_axis_result_tvalid signals.
READY_OUT Output 1 bit BIT
Ready output, active high. Indicates converter is ready to accept new input. Maps to AND of all s_axis_a_tready signals.

Properties

Property window

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Number of time-multiplexed phases (parallel conversion units). Range: 1 – 32. Higher values increase throughput proportionally but consume more FPGA resources (N instances of the Xilinx IP).

Default: 4

Range: 1 – 32

Input Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit for input

Input floating-point format:

  • Single → IEEE 754 single precision (32-bit): 8 exp + 24 mantissa
  • Double → IEEE 754 double precision (64-bit): 11 exp + 53 mantissa

Internally mapped to A_Precision_Type, C_A_Exponent_Width, and C_A_Fraction_Width in the Xilinx Floating Point IP configuration.

Default: Single

Options: Single Double

Integer part n-bit IntLength

Number of bits in the integer part of the output

Number of bits in the integer part of the output ($I$). Range: 0 – 64. This sets the Result Exponent Width in the Xilinx IP. Determines the representable integer range of the fixed-point output.

Default: 32

Range: 0 – 64

Fractional part n-bit FractLength

Number of bits in the fractional part of the output

Number of bits in the fractional part of the output ($F$). Range: 0 – 64. This sets the Result Fraction Width in the Xilinx IP. Determines the precision of values below 1.0 in the fixed-point output.

Default: 0

Range: 0 – 64

Functional description

The component wraps the Xilinx Floating Point IP (operation type: Float_to_fixed) and replicates it N times (where N = TM Factor) to support time-multiplexed data streams.

Input modes

The input F is always TM, with width (Exponent + Mantissa) × TMFactor:

  • Single precision: 32 bits per phase (8 exp + 24 mantissa)
  • Double precision: 64 bits per phase (11 exp + 53 mantissa)

Output

The output A is always TM, with width (IntLength + FractLength) × TMFactor, where each phase produces a fixed-point value with the configured number of integer and fractional bits.

Data valid and ready handshake

  • CE (input): Clock enable, controls all phases together
  • DV (output): Data valid, asserted when all phases have valid output
  • READY_OUT (output): Ready to accept new input (AND of all phase ready signals)
  • READY_IN (input): Downstream ready signal

Mathematical background

For a floating-point input $f$ in IEEE 754 format, the conversion produces a fixed-point value:

$$ a = \text{round}(f \times 2^{-F}), $$

where $F$ is the number of fractional bits (FractLength). The result is represented with IntLength integer bits and FractLength fractional bits.

The output range is:

  • Signed: $[-2^{I-1}, 2^{I-1} - 2^{-F}]$
  • Unsigned: $[0, 2^{I} - 2^{-F}]$

where $I$ = IntLength.

Timing

The Xilinx Floating Point IP has a fixed latency of 7 clock cycles per phase:

Property Latency (clock cycles)
Float to Fixed 7

Total system delay: T_delay = 7 × T_CLK.

In TM mode, all phases operate in parallel with the same latency, producing TMFactor outputs per cycle after the initial pipeline fill.

Typical use cases

  • Converting floating-point DSP results to fixed-point for data logging
  • Interface between floating-point and fixed-point processing stages
  • DAC data preparation from floating-point calculations
  • Multi-channel signal processing with time-multiplexed data acquisition

Waveform example

Example with TM Factor = 4, Single precision, IntLength = 16, FractLength = 0.

Note: 7 clock cycles of latency from input to output. Fractional parts are truncated.