Block Preview

Introduction

The Baseline Restorer block performs real-time baseline estimation on a single-sample input signal. Its main function is to compute the average (baseline) of the incoming signal samples over a defined integration period, and to pause this calculation when an event (trigger) is detected.

This ensures that transient signal excursions (pulses) do not bias the baseline estimation, which is critical for accurate pulse-height analysis in spectroscopy applications.

This is the non-time-multiplexed version of the baseline restorer, processing one sample per clock cycle.

Pin Description

DATA_IN Input WordWidth bit BIT VECTOR
Input signal whose baseline has to be calculated. Width is WordWidth bits.
Default: Must be connected
TRIGGER Input 1 bit BIT
Input signal indicating a pulse event. When HIGH, suspends baseline calculation for the duration specified by BL_HOLD.
Default: 0
M_LENGTH Input 1 bit INT
Exponent for the baseline averaging window size. The number of samples in the average is 2^M_LENGTH. Minimum value: 3 (8 samples), Maximum: limited by MaxLength property. Example: M_LENGTH=9 gives 512 samples.
Default: 9
BL_HOLD Input 1 bit INT
Number of clock cycles during which baseline calculation is suspended after a trigger. Hold time = BL_HOLD × clock_period. Example: BL_HOLD=100, clock=10ns → hold=1µs.
Default: 550
FLUSH Input 1 bit BIT
Input signal to reset and restart the baseline calculation. When HIGH, clears the accumulator and starts a fresh baseline computation.
Default: 0
CE Input 1 bit BIT
Clock enable for the baseline calculation process. When LOW, the block pauses computation.
Default: 1
CLK Input 1 bit BIT
System clock input. All internal operations are synchronous to the rising edge of CLK.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous reset input. Clears all internal state and restarts baseline computation.
Default: Default Board Reset
BASELINE Output WordWidth bit BIT VECTOR
Output signal carrying the computed baseline value. Width equals WordWidth bits (same as input width).
BASELINE_VALID Output 1 bit BIT
Output flag indicating when the baseline computation is valid. Goes HIGH after the first complete averaging window has been processed.
HOLD_TIME Output 48 bit BIT VECTOR
48-bit counter showing the cumulative time spent in hold state. Useful for monitoring dead-time in high-rate applications.
RUNNING_NOT_HOLD Output 1 bit BIT
Status output indicating the block’s operating state. HIGH when actively integrating samples, LOW when in hold (suspended) state.

Properties

Property window

Word Width WordWidth

Width of the input data in bits

Bit-width of the input and output data signals. Applies to DATA_IN and BASELINE signals. Acceptable range: 4 … 32, default 16.

Default: 16

Range: 4 – 32

Maximum Length MaxLength

Maximum number of samples for the moving average

Maximum number of samples that can be used for baseline calculation. Determines the maximum allowed value for M_LENGTH. Available values: 1024, 2048, 4096, 8192, default 1024.

Default: 1024

Options: 1024 2048 4096 8192

Usage

Functional Overview

Baseline calculation principle

The figure shows:

  • TRIGGER: The trigger signal that initiates the hold period
  • BASELINE INHIBIT: The period during which baseline calculation is suspended (to exclude the pulse)
  • BASELINE LENGTH: The integration window for computing the average

How It Works

The input signal arrives through the DATA_IN port as a single sample per clock cycle. When the trigger signal (TRIGGER) goes HIGH, the baseline computation is suspended to prevent the pulse from biasing the baseline estimate.

Baseline Window Size

The baseline is computed over a number of samples defined by the M_LENGTH input. The window size is calculated using the formula:

$$ \text{Baseline Length} = 2^{\text{M_LENGTH}} $$

M_LENGTH value Number of samples
5 32
6 64
7 128
8 256
9 512
10 1024
11 2048

Hold Duration

When a trigger occurs, the computation is suspended for a duration defined by the BL_HOLD input. This value specifies the number of clock cycles during which the baseline will be inhibited.

The actual hold duration in time units is:

$$ \text{Hold Time} = \text{BL_HOLD} \times T_{clk} $$

where $T_{clk}$ is the clock period.

Example: If the clock period is 10 ns and BL_HOLD = 100, the hold duration will be: $$100 \times 10,\text{ns} = 1,\mu\text{s}$$

Timing Diagram

The diagram shows:

  • When TRIGGER goes high, the HOLD signal activates
  • During the hold period, BASELINE output remains frozen (samples are excluded)
  • After the hold period ends, baseline integration resumes and a new BASELINE value is computed

Output Signals

  • BASELINE: The computed baseline value (moving average of input samples)
  • BASELINE_VALID: Asserts HIGH when the first valid baseline has been computed after integration
  • RUNNING_NOT_HOLD: HIGH when the block is actively integrating (not in hold state)
  • HOLD_TIME: Counter showing the number of clock cycles during which the block is in hold

Typical Applications

  • Pulse-height analysis (PHA) in gamma-ray spectroscopy
  • Baseline correction for Multi-Channel Analyzers (MCA)
  • Signal conditioning for scintillator/SiPM detectors
  • Real-time DC offset removal