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Introduction

This block performs bit merging (concatenation) on standard (non-TM) data streams. It receives multiple input vectors and concatenates them into a single wider output vector.

The operation is purely combinational with zero clock latency.

Input bit ordering is configurable:

  • IN_0 LEFT: First input becomes MSBs of output
  • IN_0 RIGHT: First input becomes LSBs of output

Pin Description

IN_0 Input Variable bit BIT
IN_1 Input Variable bit BIT
OUT Output Variable bit BIT
Merged output vector (non-TM), combinational (zero latency). Width = sum of all input widths.
IN Variable (per input) bit
Input vectors (non-TM). Number of inputs = Number Of Input property. Each input can have different widths (dynamic sizing). Inputs are concatenated based on Output Order property.
Default: Must be connected

Properties

Property window

Number Of Input InputWordSize

Set the number of inputs

Number of input vectors to merge. Range: 2 – 16384. Each input can have its own width.

Default: 2

Range: 2 – 16384

Output Order OutputOrder

Order of the inputs in output vector. IN_0 LEFT option aligns the first input on the LEFT (MSB of IN0 is MSB of OUT)

Bit ordering mode:

  • IN_0 LEFT (MSBs) → First input becomes MSBs of output
  • IN_0 RIGHT (LSBs) → First input becomes LSBs of output

Default: IN_0 LEFT (MSBs)

Options: IN_0 LEFT (MSBs) IN_0 RIGHT (LBSs)

Functional description

Wire Merge concatenates N input vectors into one output vector.

Bit ordering modes

  • IN_0 LEFT (MSBs):

    • IN_0 occupies the leftmost (MSB) positions
    • IN_N-1 occupies the rightmost (LSB) positions
    • Example: IN_0=[A,B], IN_1=[C,D] → OUT=[A,B,C,D]

  • IN_0 RIGHT (LSBs):

    • IN_0 occupies the rightmost (LSB) positions
    • IN_N-1 occupies the leftmost (MSB) positions
    • Example: IN_0=[A,B], IN_1=[C,D] → OUT=[C,D,A,B]

Example

Given 4 inputs, each 2 bits:

  • IN_0 = 10, IN_1 = 11, IN_2 = 01, IN_3 = 00
  • IN_0 LEFT: OUT (8 bits) = 10110100
  • IN_0 RIGHT: OUT (8 bits) = 00011110

Timing

Purely combinational with zero latency.

Typical use cases

  • Building wide data buses from narrow signals
  • Packing bit fields into registers
  • Constructing communication protocol frames
  • Merging status flags into status words