Block Preview

Introduction

This block generates a constant fixed-point value for use in fixed-point arithmetic pipelines. Fixed-point representation stores fractional numbers as integers with an implicit binary point position.

The user specifies a floating-point value (e.g., 3.14159), and the component automatically converts it to fixed-point format based on the configured bit widths:

  • FixedBits: Integer part width (including sign bit)
  • DecimalBits: Fractional part width

Total bit width = FixedBits + DecimalBits

The output is purely combinational with zero clock latency, suitable for direct connection to fixed-point arithmetic blocks.

Pin Description

CONST Output Variable (FixedBits + DecimalBits) bit BIT VECTOR

Constant fixed-point output, always combinational (zero latency). Width: FixedBits + DecimalBits (configurable from 2 to ~2 billion bits).

The output represents a signed fixed-point number in Q-format, where the binary point is located between bit (DecimalBits-1) and bit DecimalBits.

Properties

Property window

Name Name

Set the value of the constant.

Optional custom label for the component. If specified, replaces the default title “Const Fixed Point” on the schematic symbol. Leave blank to use default.
Value Value

Set the value of the constant.

Floating-point constant value to convert to fixed-point format. Supports standard decimal notation (e.g., 3.14159, -2.5, 0.001). Use comma or period as decimal separator.

Default: 0

Fixed bits FixedBits

Set the number of bits for the integer part of the number (including sign)

Number of bits for the integer part, including the sign bit. Minimum: 1 (sign only). Determines the representable range: [-2^(FixedBits-1), 2^(FixedBits-1) - 2^(-DecimalBits)].

Default: 2

Decimal bits DecimalBits

Set the number of bits for the decimal part of the number

Number of bits for the fractional part. Determines precision/resolution: 2^(-DecimalBits). Higher values provide better fractional accuracy but require more bits. Typical range: 8 to 32.

Default: 30

Functional description

The component implements a fixed-point constant source using Q-format notation. Given a floating-point value $V$ and bit allocations, the output is:

$$ \mathrm{CONST} = \lfloor V \times 2^{D} \rceil $$

where:

  • $V$ = user-specified floating-point value
  • $D$ = DecimalBits (fractional precision)
  • $\lfloor \cdot \rceil$ = rounding to nearest integer

The result is a $(F+D)$-bit signed integer, where $F$ = FixedBits.

Q-format notation

Fixed-point numbers use Q-format: Q(F-1).D, where:

  • $F-1$ = number of integer bits (excluding sign)
  • $D$ = number of fractional bits

For example, Q1.30 has:

  • 1 sign bit + 1 integer bit = 2 FixedBits
  • 30 DecimalBits
  • Total: 32 bits
  • Range: $[-2, 2 - 2^{-30}]$
  • Resolution: $2^{-30} \approx 9.31 \times 10^{-10}$

Value conversion example

Given:

  • Value = 3.14159
  • FixedBits = 4 (1 sign + 3 integer bits)
  • DecimalBits = 12 (fractional precision)

Conversion:

  1. Scale by $2^{12}$: $3.14159 \times 4096 = 12867.5$
  2. Round: $\lfloor 12867.5 \rceil = 12868$
  3. Binary representation (16 bits): 0011001001000100
  4. Interpretation: $12868 / 4096 = 3.141601…$

Range and overflow

The representable range depends on FixedBits ($F$):

$$ \text{Range} = \left[-2^{F-1}, 2^{F-1} - 2^{-D}\right] $$

For Q1.30 (F=2, D=30):

  • Minimum: $-2^{1} = -2.0$
  • Maximum: $2^{1} - 2^{-30} \approx 1.9999999991$

Values outside this range will overflow. The VHDL compiler will truncate overflowed values during synthesis.

Precision and resolution

Fractional resolution is determined by DecimalBits ($D$):

$$ \text{Resolution} = 2^{-D} $$

Common configurations:

DecimalBits Resolution Decimal Places
8 $2^{-8} = 0.0039$ ~2-3 digits
16 $2^{-16} = 0.000015$ ~5 digits
24 $2^{-24} = 0.000000060$ ~7 digits
32 $2^{-32} = 0.00000000023$ ~10 digits

Implementation details

The VHDL implementation converts the floating-point value to fixed-point:

vhdl 
  signal CONST : STD_LOGIC_VECTOR(TotalBits-1 downto 0);
CONST <= conv_std_logic_vector(round(Value * 2^DecimalBits), TotalBits);

The conversion happens at compile time, so there is no runtime overhead.

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Constant Fixed-Point 0

The output is available immediately after FPGA configuration.

Typical use cases

  • Fixed-point arithmetic: Provide constant coefficients for filters, gains, or scaling factors
  • Mathematical constants: Define π, e, √2, or other irrational numbers with controlled precision
  • DSP pipelines: Supply fixed-point multipliers, offsets, or thresholds
  • Calibration values: Store sensor calibration constants in fixed-point format
  • Lookup table values: Precomputed sine/cosine tables or nonlinear function approximations
  • Control systems: PID controller gains (Kp, Ki, Kd) in fixed-point representation

Example configurations

Example 1: Pi constant (Q3.28) 

  Name: "PI"
Value: 3.14159265
FixedBits: 4 (1 sign + 3 integer bits)
DecimalBits: 28
Total: 32 bits
Output: Scaled value representing π

Example 2: Gain factor 0.5 (Q0.15) 

  Value: 0.5
FixedBits: 1 (sign only)
DecimalBits: 15
Total: 16 bits
Output: Exactly 0.5 in Q0.15 format

Example 3: Negative offset (Q7.24) 

  Value: -12.345
FixedBits: 8 (1 sign + 7 integer bits)
DecimalBits: 24
Total: 32 bits
Output: -12.345 in fixed-point