DAQ blocks
2D Histogram
Calculates and stores a 2D histogram (matrix) from two 16-bit input values. Ideal for PSD matrices, …
Averaged Oscilloscope
Oscilloscope Averaged is a multi–channel oscilloscope IP core for Xilinx-7 devices able to acquire …
Citiroc Frame Transfer
Event collector and PC readout endpoint for the four CITIROC 1A ASICs of the DT5550W-Citiroc1A …
Citiroc Frame Transfer - (V2)
Event collector and PC readout endpoint for the four CITIROC 1A ASICs of the DT5550W-Citiroc1A-V2 …
Custom Packet
User-defined packet readout block with graphical packet structure editor. Implements a FIFO-based …
Custom Packet DMA
User-defined packet readout block with DMA transfer support. High-speed FIFO-based list mode …
Custom Packet ESS
Custom Packet variant for the ESS (European Spallation Source) FEA framework. It uses the same …
Data Merger
Efficiently concentrates multiple data sources into a single output using a tree-based buffered …
Data Merger (ALT)
Intel/Altera build of the Data Merger: the same binary tree of two-way merger nodes with distributed …
Digitizer
Multi-channel waveform digitizer with event-driven acquisition. Captures waveforms with timestamp, …
DT5771 Digitizer
Board-pin bridge between a SciCompiler design and the digitizer engine built into the DT5771 / …
Dual Averaged Oscilloscope
Dual Averaged Oscilloscope is a multi-channel oscilloscope IP core for Xilinx-7 devices that …
Dual Oscilloscope
Oscilloscope Dual is a multi–channel oscilloscope IP core for Xilinx-7 devices able to acquire up to …
FFT Monitor
Transfers FFT real and imaginary data to the PC for magnitude and phase spectrum visualization. …
Frame Transfer (2D Distribution)
Transfers multi-channel event data (2D distributions/images) from pixelated sensors to PC. Each …
List
Simple FIFO-based data transfer block with configurable word size. Unlike Custom Packet, this is a …
List DMA
High-throughput list block for the Ultraspectra board. It behaves like the standard List — write a …
High-performance FIFO-based data transfer block using DMA channels for maximum throughput. Uses one …
List ESS
Event list block for the ESS (European Spallation Source) FEA framework. On every TRIG edge it …
Logic Analyzer
Digital oscilloscope for FPGA signals. Captures multiple digital traces simultaneously with …
Oscilloscope
Multi-channel oscilloscope IP core for Xilinx-7 devices with up to 32 analog input channels plus 4 …
Oscilloscope TM
The Oscilloscope TM is a waveform digitizer designed for time-multiplexed (TM) signals, allowing the …
Petiroc Frame Transfer
Event builder and host readout endpoint for up to four PETIROC-2A chips. It round-robins over the …
Priority Switch
Two-way single-word switch with a hard priority channel. Forwards data from a regular IN channel …
Round Robin Arbiter
Multiplexes multiple data channels onto a single output using Round Robin arbitration. Essential for …
Round Robin Arbiter (FIFO)
Multiplexes multiple data channels onto a single output with integrated input FIFOs. Provides …
Spectrum (1D Histogram)
1D histogram block that accumulates input values into configurable bins. When connected to energy …
UDP Streamer
High-speed 10G Ethernet UDP streaming interface. Streams user data at line rate via UDP packets over …
Word Deserializer
Narrow-to-wide word gearbox (inverse of the Word Serializer). Collects several narrow input chunks - …
Word Serializer
Wide-to-narrow word gearbox. Takes one wide input word (single DV_IN pulse) and streams it out as …
X2730 Digitizer
Waveform readout block for the X2730 board. Uses the high-speed DMA engine and DDR4 memory to …
X2730 List (DPP)
List-mode data acquisition block for the X2730 board. Transfers events with parameters and optional …
X2740 Digitizer
Waveform readout block for X2740/X2745 boards. Uses the high-speed DMA engine and DDR4 memory to …
X2740 List (DPP)
List-mode data acquisition block for X2740/X2745 boards. Transfers events with parameters and …
X2751 Digitizer
Waveform readout block for the X2751 board. Uses the high-speed DMA engine and DDR4 memory to …
X2751 List (DPP)
List-mode data acquisition block for the X2751 board. Transfers events with parameters and optional …