Constant Bit-Vector [TM]
Time-multiplexed constant bit-vector source. Generates fixed bit-vector values across multiple TM phases (2-32). Supports hexadecimal (0x…), binary (0b…), and decimal formats. Can provide same value for all phases or different values per phase. Zero latency, pure combinational output.
Introduction
This block generates constant bit-vector values for time-multiplexed (TM) data streams. It produces fixed bit patterns across multiple TM phases, with each phase receiving its own configurable constant value.
The component supports two operating modes:
- Same value for all phases: One constant replicated across all TM phases
- Different values per phase: Unique constant for each TM phase
The TM Factor property (2-32) determines how many parallel constant values are generated per clock cycle.
The output is purely combinational with zero clock latency, suitable for direct use in TM signal processing pipelines.
Pin Description
Constant bit-vector output, always TM (time-multiplexed).
Width: BitSize × TM Factor bits.
Each TM phase occupies a contiguous slice of BitSize bits within the output bus. The output is combinational (zero latency) and available immediately after FPGA configuration.
TM phase ordering: Phase 0 occupies LSBs, Phase N-1 occupies MSBs.
Properties
Set the number of bits for each phase of the TM constant signal
Number of bits per TM phase. Range: 1 to 10,000,000,000. Each phase constant is resized to this width. Total output width = BitSize × TM Factor.Default: 8
Time Multiplexing factor (number of phases)
Time-multiplexing factor (number of parallel phases). Allowed values: 1 to 32. Determines how many constant values are generated per clock cycle. Must match downstream TM components.Default: 4
Range: 1 – 32
If true, the same constant value is used for all TM phases. If false, specify different values for each phase separated by comma, semicolon or space
If True, use a single Value for all TM phases (replicated). If False, provide exactly TMFactor comma/semicolon/space-separated values (one per phase). Mismatch causes compilation error.Default: True
Set the value of the constant. If ‘Same for all phases’ is true: Use single value (e.g., 0x100 or 256) If ‘Same for all phases’ is false: Use comma/semicolon/space separated values (e.g., 0x1,0x2,0x3,0x4) Use 0x
Default: 0
Functional description
The component implements a time-multiplexed constant bit-vector source in VHDL. For TM Factor = $N$, the output contains $N$ constant values:
$$ \mathrm{OUT}(t) = [V_0, V_1, V_2, \ldots, V_{N-1}] $$
where each $V_i$ is a constant bit-vector of width BitSize.
TM Factor and phase assignment
The TM Factor determines the number of parallel constant phases:
| TM Factor | Phases per Clock | Total Output Width |
|---|---|---|
| 2 | 2 | BitSize × 2 |
| 4 | 4 | BitSize × 4 |
| 8 | 8 | BitSize × 8 |
| 16 | 16 | BitSize × 16 |
| 32 | 32 | BitSize × 32 |
Each phase occupies a contiguous slice of the output bus:
- Phase 0: bits
[BitSize-1 : 0] - Phase 1: bits
[2*BitSize-1 : BitSize] - Phase N-1: bits
[N*BitSize-1 : (N-1)*BitSize]
Operating modes
Mode 1: Same value for all phases
When SameForAllPhases = True, a single value is replicated:
Value: 0xFF
TM Factor: 4
BitSize: 8
Output (32 bits): [0xFF, 0xFF, 0xFF, 0xFF]
Phase0 Phase1 Phase2 Phase3
Mode 2: Different values per phase
When SameForAllPhases = False, provide comma/semicolon/space-separated values:
Value: 0x10, 0x20, 0x30, 0x40
TM Factor: 4
BitSize: 8
Output (32 bits): [0x10, 0x20, 0x30, 0x40]
Phase0 Phase1 Phase2 Phase3
Important: The number of values must exactly match the TM Factor, or a compilation error will occur.
Value formats
Each phase value supports three input formats:
-
Hexadecimal (
0xprefix):Value: 0xFF, 0x100, 0xABCD -
Binary (
0bprefix):Value: 0b10101010, 0b11110000, 0b00001111 -
Decimal (no prefix):
Value: 255, 1024, 65535
Formats can be mixed within a multi-value specification:
Value: 0xFF, 256, 0b11110000, 0x1000
Bit width and resizing
Each phase value is automatically resized to BitSize bits using the same rules as the non-TM version:
- Truncation: If value > 2^BitSize - 1, MSBs are discarded
- Zero-extension: If value < 2^BitSize, zeros are prepended
Example:
Value: 0x1FF (9 bits needed)
BitSize: 8
Result: 0xFF (MSB truncated)
Implementation details
The VHDL implementation concatenates all phase values into a single bus:
vhdl
signal CONST : STD_LOGIC_VECTOR(TotalWidth-1 downto 0);
CONST <= VV(N-1) & VV(N-2) & ... & VV(1) & VV(0);
where each VV(i) is the converted bit-vector for phase $i$.
Timing
The component is purely combinational with zero latency:
| Property | Latency (clock cycles) |
|---|---|
| Constant Bit-Vector [TM] | 0 |
All TM phases are available immediately (no pipeline delay).
Typical use cases
- TM test patterns: Generate known bit sequences for TM pipeline verification
- TM lookup tables: Provide constant indices or addresses for parallel lookups
- TM protocol constants: Define fixed headers or identifiers for multiple streams
- TM bit masks: Create phase-specific masking patterns for parallel processing
- TM initialization: Supply default or reset values to TM data paths
- TM waveform generation: Create fixed digital waveforms across TM phases
Example configurations
Example 1: Same value, all phases (TM=4)
BitSize: 16
TMFactor: 4
SameForAllPhases: True
Value: 0x1234
Output (64 bits):
Phase 0: 0x1234
Phase 1: 0x1234
Phase 2: 0x1234
Phase 3: 0x1234
Example 2: Different values per phase (TM=4)
BitSize: 8
TMFactor: 4
SameForAllPhases: False
Value: 0xAA, 0x55, 0xFF, 0x00
Output (32 bits):
Phase 0: 0xAA (10101010)
Phase 1: 0x55 (01010101)
Phase 2: 0xFF (11111111)
Phase 3: 0x00 (00000000)
Example 3: Mixed value formats (TM=2)
BitSize: 12
TMFactor: 2
SameForAllPhases: False
Value: 0b111100001111, 0xFFF
Output (24 bits):
Phase 0: 0xF0F (111100001111)
Phase 1: 0xFFF (111111111111)
Example 4: Ascending pattern (TM=8)
BitSize: 4
TMFactor: 8
SameForAllPhases: False
Value: 0, 1, 2, 3, 4, 5, 6, 7
Output (32 bits): [0, 1, 2, 3, 4, 5, 6, 7]
Use case: Sequential addressing or counting pattern