Xilinx
TM
Block Preview

Introduction

This block computes the exponential function (e^x) of IEEE 754 floating-point values using the Xilinx Floating Point IP core. The component supports Time Multiplexing (TM): multiple parallel computation units (phases) share the same clock cycle.

On every rising edge of CLK, if DIN_VLD = 1 and DOUT_RDY = 1:

$$ \mathrm{DOUT}(n) = e^{\mathrm{DIN}(n)} = \exp\bigl(\mathrm{DIN}(n)\bigr) $$

Pin Description

DIN Input Variable bit TM
Floating-point input, always TM.
Default: Must be connected
DIN_VLD Input 1 bit BIT
Input data valid.
DIN_RDY Output 1 bit BIT
Input ready output.
CLK Input 1 bit BIT
Global clock.
Default: Default Board Clock
DOUT Output Variable bit TM
Exponential output. Valid after 21 cycles.
DOUT_VLD Output 1 bit BIT
Output data valid.
DOUT_RDY Input 1 bit BIT
Downstream ready signal.

Properties

Property window

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Number of TM phases (1 – 32).

Default: 4

Range: 1 – 32

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Single or Double precision.

Default: Single

Options: Single Double

DSP Usage DSPUsage

DSP Usage. Single precision: No [0], Medium [1], Full[2], Max[7]. Double precision: No[0], Medium [15], Full[26]

  • No_Usage, Medium_Usage, Full_Usage Single: 0/1/2 DSPs; Double: 0/15/26 DSPs

Default: Full_Usage

Options: No_Usage Medium_Usage Full_Usage

RAM Usage RAMUsage

Use LUT or BRAM in FPGA

  • No_Usage → Use LUTs
  • Full_Usage → Use BRAM lookup tables

Default: Full_Usage

Options: No_Usage Full_Usage

Functional description

Wraps Xilinx Floating Point IP (operation type: Exponential) with N parallel instances for TM support.

Input and Output

  • Input DIN is always TM
  • Output DOUT is always TM, same width

Mathematical background

The exponential function:

$$ y = e^x = \exp(x) $$

Properties:

  • $e^0 = 1$
  • $e^1 = e \approx 2.71828$
  • $e^{x+y} = e^x \cdot e^y$
  • $\frac{d}{dx}e^x = e^x$

Timing

Fixed latency of 21 clock cycles per phase.

Property Latency (cycles)
Exponential 21

DSP and RAM Usage

  • DSP Usage: Single: No [0], Medium [1], Full[2]; Double: No[0], Medium [15], Full[26]
  • RAM Usage: No_Usage or Full_Usage (uses BRAM for lookup tables)

Typical use cases

  • Gaussian function computation
  • Neural network activation functions
  • Statistical distributions
  • Signal envelope generation
  • Exponential decay models