Xilinx
HLS
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Introduction

The Complex Swap I/Q block exchanges the two channels of a complex baseband sample:

      OUT_I[n] = IN_Q[n]
    OUT_Q[n] = IN_I[n]

Equivalently, with X = IN_I + j*IN_Q,

      OUT = IN_Q + j*IN_I = j * conj(X)

This is a pure wire crossover: no arithmetic, no bit growth. Data is signed two’s complement.

Pin Description

IN_I Input InputSize bit BIT VECTOR
In-phase (I) input sample. Signed, Input Bit Width bits.
Default: Must be connected
IN_Q Input InputSize bit BIT VECTOR
Quadrature (Q) input sample. Signed, Input Bit Width bits.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
HLS synchronous reset (ap_rst). Default: Global reset.
Default: Default Board Reset
OUT_I Output InputSize bit BIT VECTOR
In-phase (I) output = IN_Q. Signed, InputSize bits.
OUT_Q Output InputSize bit BIT VECTOR
Quadrature (Q) output = IN_I. Signed, InputSize bits.

Properties

Property window

Input Bit Width InputSize

Bit width of each I/Q sample (signed).

Bit width of each signed I / Q sample. Range 4 to 32, default 16. The output width equals the input width.

Default: 16

Options: 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Usage

Bit widths

Data is signed two’s complement and the width is unchanged.

  • IN_I, IN_Q : signed InputSize bits.
  • OUT_I, OUT_Q : signed InputSize bits.

Interpretation

Swapping I and Q is equivalent to j * conj(X): it conjugates the phasor (flipping the spectrum) and then rotates it by +90 degrees. It is the simplest way to correct an inverted I/Q wiring convention between two blocks that disagree on the sign of the imaginary axis.

Latency and throughput

  • #pragma HLS PIPELINE II=1 : one sample pair per clock.
  • 1-clock latency.
  • All data ports use the ap_none interface (no ready/valid handshake); the core is free-running (ap_ctrl_none).

Reset

RESET is the HLS synchronous reset (ap_rst).

Typical applications

  • I/Q convention fix between blocks with opposite imaginary-axis sign.
  • Spectrum flip combined with a 90-degree relabel (j*conj(X)).
  • Quick +/-90-degree rotate without a multiplier.

Resources & Timing

  • Latency: 1 clock cycle

  • Throughput: 1 sample per clock (II=1)

Zero DSPs and zero LUTs of logic: a pure wire crossover. Implemented with Vitis HLS. Free-running core (ap_ctrl_none), no handshake logic.