DSP - BLOCK PEAK COUNT TM
TM (time multiplexed) twin of Block Peak Count: TM Factor (2..16) independent channels packed on one wide bus, each counting the pulses that crossed a broadcast THRESHOLD with a Schmitt trigger - one count per EXCURSION, not per noisy rattle - over its own block of N = 2^EXP samples (EXP on a runtime pin, shared by every lane). One shared frame - one EXP, one IN_DV, one OUT_DV per block - with a per-lane Schmitt detector and counter at II=1 and ONE serial tail serving the lanes one after the other, so the tail resources stay those of the scalar block whatever the lane count. Lane 0 sits in the LOW bits of every packed bus. Same per-lane numbers as the scalar twin, bit for bit. Optional shared BUSY / INTEGRATING / SAMPLE_COUNT status outputs.
Introduction
Per lane, over each block of N samples:
Per lane: a Schmitt trigger with upper level = THRESHOLD and lower level
= THRESHOLD - |HYSTERESIS| counts ONE peak per excursion, on its rising
edge; the lane’s signal must fall back through the lower level before
another can be counted. PEAK_RATE = peaks / N is an exact shift.
Comparisons are STRICT.
This is the time multiplexed (TM) twin of the scalar Block Peak Count block: TM Factor independent channels packed on one wide bus, each counting the level excursions of its own block of N consecutive samples. Nothing is shared between the channels except the frame and the two level pins.
The TM contract
INis TM Factor lanes of input width bits each, lane 0 in the LOW bits (lane 0 is the oldest sample of the clock) - the same packing as every other TM block in the toolchain. Each lane is an independent channel: its own Schmitt state, its own counter, its own result.THRESHOLDandHYSTERESISare ONE SCALAR BROADCAST PIN EACH (in the INPUT lane format, latched per block likeEXP): one reference pair for every lane, so a block’s counts are never a mixture of two thresholds - in any lane. Lanes needing different thresholds need scalar blocks.- THE SCHMITT STATE IS PER LANE: a lane’s detector arms and re-arms on
ITS OWN samples only, and - exactly like the scalar twin - it CARRIES
ACROSS BLOCK BOUNDARIES per lane, so a pulse that straddles a boundary
is counted once, not twice; only
RESETclears it. - ONE shared
EXPpin, ONEIN_DV, one frame: all lanes start and end their blocks on the same accepted clocks.BUSY,INTEGRATINGandSAMPLE_COUNTtherefore stay scalar -SAMPLE_COUNTcounts per-lane samples, which are identical in every lane by construction. - Accumulation runs at II=1 on the packed bus - per lane it is two
comparisons and a counter, no multiplier anywhere. The serial
post-processing is ONE shared engine serving the lanes one after the
other; ONE
OUT_DVper block, after the LAST lane finishes, with all output lanes staged and committed together on that clock, so every packed output moves on theOUT_DVclock and no other.
N is a runtime input: the block size is $N = 2^{\mathrm{EXP}}$, EXP clamped to Max Block Exponent and latched on the first accepted sample of a block, so a change takes effect on the NEXT block - for every lane at once. Because N is a power of two, PEAK_RATE = peaks / N is an exact shift in every lane.
When to use this instead of TM Factor scalar blocks
One TM block and TM Factor scalar blocks compute the same numbers. The TM block pays the per-lane detector state (unavoidable either way) but shares ONE frame, ONE control FSM and ONE serial tail across all lanes. The price is tail latency (TM Factor times the scalar tail - trivial here) and the coupling of the frame AND of the levels: all lanes share the same block length, the same sample cadence and the same THRESHOLD / HYSTERESIS pair. Channels that need different block sizes or different thresholds need scalar blocks.
Pin Description
IN_DV is high.
Properties
Number of INTEGER bits of the input sample (per lane) (the sign, when present, uses one of them).
Integer bits of ONE LANE of the input (the sign, when present, uses one of them). 1..64. Default 16. THRESHOLD and HYSTERESIS share this format.Default: 16
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Number of FRACTIONAL bits of the input sample (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.
Fractional bits of one lane of the input. 0..64, total lane width 2..64 bits. Default 0.Default: 0
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Select whether the input sample (per lane) is signed (two’s complement) or unsigned.
SIGNED (two’s complement) or UNSIGNED lanes. Default SIGNED. Applies to every lane and to both level pins.Default: SIGNED
Options: UNSIGNED SIGNED
Number of INDEPENDENT time-multiplexed channels packed on the IN bus and on every result bus. Lane 0 occupies the LOW bits (lane 0 = the oldest sample of the clock), the same packing as every other TM block. All lanes share one EXP / IN_DV / frame; each lane gets its own accumulators, but the serial post-processing is ONE engine serving the lanes one after the other, so the tail latency (and the minimum usable EXP) grows with this factor.
Number of independent channels packed on the buses, 2..16. Default 4. Multiplies the IN width, every packed output width AND the serial tail length (the shared tail serves the lanes one after the other), so it also raises the minimum usable EXP.Default: 4
Options: 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Largest block-size exponent the accumulators are sized for: the block can be up to 2^MaxBlockExponent samples long. The EXP input is clamped to this value at run time. Raising it widens the internal accumulators, and ON THE BLOCKS WHOSE SERIAL ENGINES ARE SIZED FROM THOSE ACCUMULATORS (Coefficient of Variation, SNR, Skewness, Kurtosis, Correlation, Autocorrelation, Linear Regression) it also LENGTHENS THE SERIAL TAIL – even when the runtime EXP is small. Keep it at the largest block you actually use. The default of 20 covers blocks of up to 1048576 samples.
Largest block-size exponent the per-lane counters are sized for; the EXP input is clamped to it at run time. It sets each PEAK_COUNT lane’s width to MaxBlockExponent + 1 bits. 1..31, default 20.Default: 20
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
YES: the the PEAK_COUNT output (per lane, packed) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the packed PEAK_COUNT bus exists. Default YES.Default: YES
Options: NO YES
YES: the the PEAK_RATE output (per lane, packed) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the packed PEAK_RATE bus exists. Default YES.Default: YES
Options: NO YES
Number of INTEGER bits of the PEAK_RATE output (per lane) (the sign, when present, uses one of them).
Integer bits of ONE LANE of PEAK_RATE. Default 1.Default: 1
Options: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Number of FRACTIONAL bits of the PEAK_RATE output (per lane), i.e. the bits to the right of the binary point. Total width = integer + fractional bits, and must not exceed 64.
Fractional bits of one lane. Default 15.Default: 15
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Select whether the PEAK_RATE output (per lane) is signed (two’s complement) or unsigned.
Default UNSIGNED (a rate is non negative by construction).Default: UNSIGNED
Options: UNSIGNED SIGNED
YES: the BUSY (high from the first sample of a block until its result is out – it COVERS THE SERIAL TAIL, and its last high clock IS the OUT_DV pulse) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared BUSY pin exists. Default NO.Default: NO
Options: NO YES
YES: the INTEGRATING (high only while the block is ACCUMULATING; it drops as soon as the N-th sample has been taken and the tail starts, so BUSY-and-not-INTEGRATING means ‘computing’) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared INTEGRATING pin exists. Default NO.Default: NO
Options: NO YES
YES: the SAMPLE_COUNT (32 bit, how many samples have been accumulated so far in the current block: 1 after the first, N after the N-th. It is NOT cleared at the block end – it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail, so at OUT_DV it reads how far into the next block the input has already got, NOT N. To capture the length of the block being presented, latch SAMPLE_COUNT on the clock INTEGRATING falls – that one always reads N) pin is present. NO: the pin AND all of its logic are removed BEFORE synthesis, so nothing is paid for it.
YES: the shared 32 bit SAMPLE_COUNT pin exists. Default NO.Default: NO
Options: NO YES
ROUND: round to nearest when a result has to be requantised into a coarser output format. TRUNCATE: drop the bits (cheaper, adds a negative bias).
ROUND: round to nearest at each lane’s PEAK_RATE requantisation (PEAK_COUNT is never requantised). TRUNCATE: drop the bits. Default ROUND.Default: ROUND
Options: TRUNCATE ROUND
YES: clip to the largest representable value of each output format (symmetric for signed formats). NO: wrap around.
YES: clip each PEAK_RATE lane to its format (PEAK_COUNT cannot overflow and ignores this). NO: wrap. Default YES.Default: YES
Options: NO YES
Accuracy, per lane
Each lane is BIT EXACT, like the scalar twin: PEAK_COUNT is a plain
per-lane counter, Max Block Exponent + 1 bits per lane, which CANNOT
overflow (a lane’s count can never exceed N) and is never requantised -
Rounding and Saturation do not touch it. PEAK_RATE is exact up to
the single final requantisation per lane: PEAK_COUNT * 2^-EXP produced by
a shift of an exact integer. The harness demands tolerance 0 per lane.
Timing: the TM latency contract
OUT_DV pulses ONCE per block, L clocks after the clock on which the
N-th sample was accepted, where
$$ L = 1 + \mathrm{TM} $$
(BPCT_TAIL in the core). Everything is evaluated inside the window, so
the shared tail is one requantise clock per lane plus the registered
OUT_DV - the family’s lane-multiplexed rule
$L_{tm}(e) = \mathrm{TM},(L_{scalar}(e)-1)+1$ with $L_{scalar} = 2$. It is
a CONSTANT: 5 clocks at the default TM Factor of 4, 17 at TM 16.
The family drop rule applies with the TM tail: the tail of one block must
finish before the NEXT block completes, $2^{{\mathrm{{EXP}}}} \ge L$, or the
completing block’s result is silently DROPPED (no OUT_DV, accumulators
unaffected, no error pin). The TM tail makes the minimum usable EXP larger
than the scalar twin’s (EXP >= 3 at TM 4, EXP >= 5 at TM 16, against the
scalar’s 1) - the compiler prints both the worst-case tail and
the minimum EXP in the compilation log, and the property window refuses a
configuration whose minimum exceeds Max Block Exponent.
Knowing where the block is: BUSY, INTEGRATING and SAMPLE_COUNT
Identical to the scalar family, and SHARED by all lanes: INTEGRATING is
high exactly while the block is accumulating (it dips one clock per block
boundary on a continuous stream), BUSY also covers the (TM-long) tail and
its last high clock IS the OUT_DV pulse, SAMPLE_COUNT reads 1 after the
first accepted sample and N after the N-th.
SAMPLE_COUNTis NOT cleared at the block end - it holds N until the NEXT block’s first accepted sample takes it back to 1. On a CONTINUOUS stream that happens DURING the serial tail (which on a TM block is TM Factor times longer), so atOUT_DVit reads how far into the next block the input has got, NOT N. The clock that always reads N is the oneINTEGRATINGfalls on - latch it there.
Verification
The core is regression tested by a host-side csim harness
(tb/block-ops-tm/run_tb_tm.ps1) with per-lane goldens computed by
gen_golden_tm.py in exact rational arithmetic ON EACH LANE’S STREAM ALONE
(lanes deliberately carry different signals - the generator refuses
identical lanes), plus the strongest available lane-independence check:
after every run, the SCALAR twin is replayed on each lane’s stream by
itself and lane k of every TM result must match it BIT FOR BIT. The
status waveform is checked clock by clock, every packed output is checked
to move only on OUT_DV, and the TM-specific mutant classes (shared
detector state, lane swaps, wrong-lane tail reads, early commit, drop
rule) are killed. What no host harness can prove - that Vitis accepts and
schedules the core at II=1 - is stated in AGENT/block_ops.log, not
silently implied.