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Introduction

The UART block implements a Universal Asynchronous Receiver/Transmitter for serial communication without a shared clock signal.

UART uses only two wires for bidirectional communication:

  • TX - Transmit data output (master to slave)
  • RX - Receive data input (slave to master)

Key features:

  • Configurable baud rate (300 to 3,000,000 bps)
  • Configurable data width (5-9 bits)
  • Optional parity (None, Even, Odd)
  • Independent TX and RX channels
  • Error detection for framing and parity errors

Pin Description

DATA_IN Input 8 bit BIT VECTOR
START_TX Input 1 bit BIT
RX Input 1 bit BIT
Serial receive input. Connect to the remote device’s TX output. Idle state is HIGH.
Default: Must be connected
CLK Input 1 bit BIT
System clock input. Used to generate baud rate timing. Must be high enough for desired baud rate (at least 16x baud rate). Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Default: Default Board Reset
DATA_OUT Output 8 bit BIT VECTOR
DV Output 1 bit BIT
Data Valid output, active high. Pulses high for one CLK cycle when received data is ready. Check Error RX to verify data integrity.
BUSY_TX Output 1 bit BIT
BUSY_RX Output 1 bit BIT
ERROR_RX Output 1 bit BIT
TX Output 1 bit BIT
Serial transmit output. Connect to the remote device’s RX input. Idle state is HIGH.
Data In Variable bit
Parallel data to transmit. Width: Data Bit Size (5-9 bits). Data is latched when Start TX goes high.
Default: Must be connected
Start TX 1 bit
Initiate transmission. When HIGH, latches Data In and begins serial transmission. Should be pulsed high for at least one CLK cycle. Do not assert while Busy TX is high.
Reset 1 bit
Asynchronous reset, active high. When HIGH, resets the UART to idle state. Must be LOW for normal operation. Default: Global reset.
Data Out Variable bit
Parallel received data. Width: Data Bit Size (5-9 bits). Valid when DV pulses high. Remains stable until next reception completes.
Busy TX 1 bit

Transmit busy status.

  • LOW: Ready to accept new data
  • HIGH: Transmission in progress
Busy RX 1 bit

Receive busy status.

  • LOW: Idle, waiting for start bit
  • HIGH: Reception in progress
Error RX 1 bit

Receive error flag. Goes HIGH if any error detected:

  • Start bit error (not LOW)
  • Parity mismatch
  • Stop bit error (not HIGH) Valid when DV pulses.

Properties

Property window

Data Bit Size BitSize

Set the number of data bits per word (5-9)

Default: 8

Range: 5 – 9

CLK Pin Frequency (MHz) ClockFreq

Set the input clock frequency in MHz

Default: 100

Range: 1 – 500

Baud Rate BaudRate

Set the communication baud rate in bits per second

Communication speed in bits per second. Both transmitter and receiver must use the same rate.

Standard baud rates:

  • 9600: Common for slow devices
  • 19200: Legacy standard
  • 38400: Moderate speed
  • 57600: Faster legacy
  • 115200: Most common modern default
  • 230400: High speed
  • 460800: Very high speed
  • 921600: Maximum standard rate
  • 1000000+: Non-standard high speeds

Actual rate may differ slightly due to integer clock division.

Default: 115200

Range: 300 – 3000000

Parity Parity

Select parity mode for error detection

Error detection mode.

  • None: No parity bit, 1 stop bit
  • Even: Parity bit makes total 1s even
  • Odd: Parity bit makes total 1s odd

Parity adds one bit to each frame and provides basic error detection. For critical applications, consider higher-level protocols with CRC.

Default: None

Options: None Even Odd

Name Name
Instance name for this UART component. Used for signal naming and identification.
DataBitSize DataBitSize

Number of data bits per word (5-9). Most common setting is 8 bits.

Standard configurations:

  • 7 bits: ASCII text (legacy)
  • 8 bits: Most common, binary data
  • 9 bits: With address/data flag (Multidrop)
CLKPinFrequency CLKPinFrequency

Frequency of the CLK input in MHz. Used to calculate baud rate timing.

Must be at least 16 times the baud rate for proper operation. For 115200 baud, minimum CLK is ~1.85 MHz.

Typical values:

  • 50 MHz: V2495 default
  • 80 MHz: DT5550 default
  • 100-200 MHz: High-speed designs

Functional description

UART transmits data asynchronously without a clock signal. Both transmitter and receiver must be configured for the same baud rate and data format.

Data Frame Structure

Each data frame consists of:

  1. Start bit: Line goes LOW to signal start of transmission
  2. Data bits: 5-9 bits, LSB first
  3. Parity bit (optional): Even or odd parity for error detection
  4. Stop bit: Line returns HIGH for at least one bit period

Baud Rate

The baud rate determines how many bits are transmitted per second. Common standard rates include:

Baud Rate Bit Period
9600 104.2 us
19200 52.1 us
38400 26.0 us
57600 17.4 us
115200 8.7 us
230400 4.3 us
460800 2.2 us
921600 1.1 us

The UART generates internal timing from the CLK input using:

$$ T_{bit} = \frac{f_{CLK}}{BaudRate} $$

Oversampling

The receiver uses 16x oversampling to accurately detect the center of each bit, providing tolerance for baud rate mismatch between devices (typically up to 3% difference is acceptable).

Parity

Parity provides simple error detection:

  • None: No parity bit transmitted
  • Even: Parity bit makes total number of 1s even
  • Odd: Parity bit makes total number of 1s odd

If received parity doesn’t match calculated parity, Error RX goes high.

Transmission Flow

  1. Load data on Data In
  2. Pulse Start TX high
  3. Busy TX goes high during transmission
  4. TX outputs start bit, data bits, parity (if enabled), stop bit
  5. Busy TX goes low when complete

Reception Flow

  1. RX line monitored for start bit (HIGH to LOW transition)
  2. Busy RX goes high during reception
  3. Data bits sampled at center of each bit period
  4. Parity checked (if enabled)
  5. Stop bit verified
  6. DV pulses high when data is ready
  7. Read received data from Data Out
  8. Check Error RX for framing or parity errors

Reset Behavior

The Reset input is active high:

  • TX line held HIGH (idle)
  • Busy TX held HIGH (not ready)
  • Busy RX held LOW
  • After reset release, Busy TX goes LOW on next CLK