Xilinx
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Introduction

The block computes the square root of IEEE-754 floating-point inputs. On every rising edge of CLK, if CE = 1, the square root unit computes

$$ \mathrm{F}(n) = \sqrt{\mathrm{A}(n)}, $$

where input A and output F follow IEEE-754 single or double precision format.

The square root is implemented with the Xilinx floating_point IP core configured for Square_root operation using iterative algorithm with blocking flow control, fixed 29-cycle latency, and configurable initiation interval to trade area for throughput.

Pin Description

A Input Variable bit BIT VECTOR
Floating-point input value (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Must be non-negative (A >= 0) for valid results. Accepted when CE = 1 and READY_OUT = 1.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable (tvalid), active high. When CE = 1, input A is accepted and square root computation begins. Can be tied to ‘1’ for continuous operation.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal (tready input), active high. Indicates if downstream logic can accept new data. Can be tied to ‘1’ if backpressure is not needed.
CLK Input 1 bit BIT
Global clock. Every rising edge triggers pipeline advancement. Connected to system acquisition clock.
Default: Default Board Clock
F Output 32 bit BIT VECTOR
Floating-point square root output (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Valid when DV = 1. Result = sqrt(A).
DV Output 1 bit BIT
Data Valid output (tvalid), active high. Indicates when output F contains a valid square root. Asserts 29 clock cycles after corresponding CE = 1.
READY_OUT Output 1 bit BIT
Upstream ready signal (tready output), active high. Indicates this block can accept new input data. May deassert if II > 1 and core is busy.

Properties

Property window

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Floating-point precision for both input and output:

  • Single → 32-bit (8-bit exponent, 24-bit mantissa including implicit bit)
  • Double → 64-bit (11-bit exponent, 53-bit mantissa including implicit bit)

The operation preserves the precision format end-to-end.

Default: Single

Options: Single Double

Cycle per operation II

Number of clock cycles to execute a division. Set to 1 to perform division in realtime. Higher number reduce the area usage of the block

Initiation Interval (cycles per operation). Range: 1 - 25.

  • 1 → Fully pipelined, maximum throughput, largest area
  • 25 → Minimal area, throughput = 1/25 of maximum

Set to 1 for continuous streaming square root operations. Increase to reduce resource usage if throughput is not critical.

Default: 1

Range: 1 – 25

Functional description

The component computes the square root:

$$ F = \sqrt{A} $$

The implementation uses an iterative digit-recurrence algorithm with:

  • Exponent halving ($e’ = e/2$)
  • Mantissa square root via Newton-Raphson or similar iteration
  • Result normalization

Special cases

IEEE-754 special value handling:

  • sqrt(0) = 0
  • sqrt(1) = 1
  • sqrt(x) = NaN for x < 0 (domain error)
  • sqrt(+Inf) = +Inf
  • sqrt(NaN) = NaN (NaN propagation)

Initiation Interval (II)

The Cycle per operation property sets the initiation interval:

  • II = 1 → New operation every cycle (maximum throughput, largest area)
  • II = 25 → New operation every 25 cycles (minimum area, reduced throughput)

Higher II values reduce hardware resources (especially logic and registers) at the cost of lower throughput. For continuous streaming, choose II = 1. For infrequent square roots, larger II saves area.

Timing

The IP has a fixed 29-cycle pipeline latency regardless of II:

Clock cycle Event
0 Input A presented with CE = 1
29 Output F valid with DV = 1

With II = 1, a new operation can start every cycle (fully pipelined). With II > 1, the next operation must wait II cycles before starting.

Typical use cases

  • RMS (root-mean-square) calculations
  • Distance computation (Euclidean norm components)
  • Standard deviation in statistics
  • Magnitude normalization