Gaussian Noise Generator (GNG)
Generates true Gaussian (normal) distributed noise using a hardware PRNG. Output can be mixed with an input signal to add controllable random noise.
Introduction
The Gaussian Noise Generator (GNG) block generates true Gaussian (normally distributed) noise starting from an internal Pseudo-Random Number Generator (PRNG). The output is in signed integer format and can be combined with an input signal to add controllable random noise.
This component is useful for testing signal processing chains, simulating noisy signals, or adding dithering to signals.
Pin Description
Noise amplitude control (unsigned 16-bit). Controls the standard deviation of the Gaussian distribution.
- 0x0000: No noise
- 0xFFFF: Maximum amplitude
DC offset or signal input (unsigned 16-bit). Added to the noise output: NOISE = OFFSET + GN. Use to:
- Add a constant offset to center the noise
- Mix an external signal with the generated noise Default: 0
Output data valid indicator.
- HIGH (1): NOISE output contains valid data
- LOW (0): NOISE output is invalid (during startup/reset) Goes HIGH after pipeline fills (~13 cycles after reset).
Properties
Seed automatically generated in order to randomized the GN Noise. A new random seed is automatically generated when the component is created
Initial seed for the PRNG (3x 64-bit hexadecimal values). Determines the pseudo-random sequence. Use the EDIT button to generate new seeds. Do not manually modify - improper seeds may reduce randomness.Default: 0CA5AAA2FE8FEAC3D54678C3099CD984B262CDBFEDDC061B
Usage
Algorithm Overview
The GNG uses a Combined Tausworthe Generator (CTG) to produce uniformly distributed random numbers, followed by a polynomial interpolation stage that transforms the uniform distribution into a Gaussian distribution.
The algorithm implements the inverse cumulative distribution function (CDF) of the Gaussian distribution using piecewise polynomial approximation.
Architecture
The implementation consists of three main stages:
-
Combined Tausworthe PRNG (CTG)
- Uses three 64-bit Linear Feedback Shift Registers (LFSRs)
- XOR combination produces 64-bit uniform random values
- Initialized with a proprietary seed for maximum sequence length
-
Leading Zero Detector (LZD)
- Counts leading zeros in the random value
- Maps uniform distribution to exponential-like distribution
-
Polynomial Interpolator
- 248-entry coefficient lookup table
- Second-order polynomial approximation
- Converts to Gaussian distribution with fixed-point arithmetic
Output Characteristics
The output noise follows a Gaussian distribution:
$$ f(x) = \frac{1}{\sigma\sqrt{2\pi}} e^{-\frac{(x-\mu)^2}{2\sigma^2}} $$
where:
- $\mu$ = 0 (zero mean, before offset)
- $\sigma$ is proportional to the GAIN input
The noise is generated in signed 16-bit format with approximately 11 fractional bits (s<16,11>).
Gain Control
The GAIN input controls the noise amplitude (standard deviation):
| GAIN Value | Effect |
|---|---|
| 0x0000 | No noise output |
| 0x8000 | Half amplitude |
| 0xFFFF | Maximum amplitude |
The relationship is linear: higher GAIN values produce larger noise amplitude.
Signal Mixing
The block performs the following operation:
$$ \text{NOISE} = \text{OFFSET} + \text{GN} \times \text{GAIN} $$
where GN is the internal Gaussian noise sample. This allows:
- Adding a DC offset to the noise
- Mixing noise with an external signal (connect signal to OFFSET)
- Creating noisy versions of clean signals
Seed Configuration
The initial seed is a 48-character hexadecimal number (3x 64-bit values) that determines the random sequence. Important:
- Each seed produces a deterministic but pseudo-random sequence
- Different seeds produce statistically independent sequences
- Use the EDIT button in SciCompiler to generate new seeds
- The proprietary seed generation algorithm maximizes sequence randomness
Do not manually create seeds - always use SciCompiler’s seed generator to ensure proper statistical properties.
Timing
| Parameter | Value |
|---|---|
| Pipeline Latency | ~13 clock cycles |
| Valid Signal Delay | 4 clock cycles after internal valid |
| Throughput | 1 sample per clock cycle (when CE=1) |
The VALID output indicates when the pipeline has produced a valid noise sample after reset or after changing the CE signal.
Resources & Timing
-
Latency: ~13 clock cycles
-
Throughput: 1 sample per clock cycle