Xilinx
TM
Block Preview

Introduction

This block computes the absolute value of IEEE 754 floating-point numbers using the Xilinx Floating Point IP core. The component supports Time Multiplexing (TM): multiple parallel computation units (phases) share the same clock cycle, enabling high sample rates with zero latency.

On every rising edge of CLK, if CE = 1 and READY_IN = 1, the operator performs

$$ \mathrm{F}(n) = |\mathrm{A}(n)|, $$

where both input and output are IEEE 754 floating-point values. The TM Factor property determines how many parallel instances are instantiated.

Pin Description

A Input Variable bit TM

Floating-point input data, always TM. Width: (Exponent + Mantissa) × TMFactor

  • Single: 32 bits/phase → total 32×TMFactor
  • Double: 64 bits/phase → total 64×TMFactor IEEE 754 format input for absolute value computation.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable / Input Valid, active high. When CE = 0 the operator is stalled. Maps to s_axis_a_tvalid in the AXI Stream interface.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal, active high. Indicates that downstream logic can accept new data. Maps to m_axis_result_tready. Default: ‘1’ if not connected.
F Output Variable bit TM
Floating-point output, always TM. Width: Same as input Each phase produces |A| in IEEE 754 format. Available immediately (zero latency).
DV Output 1 bit BIT
Data Valid output, active high. Asserted when all TM phases have valid output data. Maps to AND of all m_axis_result_tvalid signals.
READY_OUT Output 1 bit BIT
Ready output, active high. Indicates operator is ready to accept new input. Maps to AND of all s_axis_a_tready signals.

Properties

Property window

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Number of time-multiplexed phases (parallel computation units). Range: 1 – 32. Higher values increase throughput proportionally but consume more FPGA resources (N instances of the Xilinx IP).

Default: 4

Range: 1 – 32

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Floating-point format for both input and output:

  • Single → IEEE 754 single precision (32-bit): 8 exp + 24 mantissa
  • Double → IEEE 754 double precision (64-bit): 11 exp + 53 mantissa

Determines precision and range of the computation.

Default: Single

Options: Single Double

Functional description

The component wraps the Xilinx Floating Point IP (operation type: Absolute) and replicates it N times (where N = TM Factor) to support time-multiplexed data streams.

Input and Output

  • Input A is always TM, with width (Exponent + Mantissa) × TMFactor
  • Output F is always TM, with the same width as input
  • Both maintain the selected precision (Single or Double)

Data valid and ready handshake

  • CE (input): Clock enable, controls all phases together
  • DV (output): Data valid, asserted when all phases have valid output
  • READY_OUT (output): Ready to accept new input (AND of all phase ready signals)
  • READY_IN (input): Downstream ready signal

Mathematical background

The absolute value operation produces the magnitude of a number:

$$ |x| = \begin{cases} x & \text{if } x \geq 0 \ -x & \text{if } x < 0 \end{cases} $$

For IEEE 754 floating-point, this is simply clearing the sign bit.

Properties:

  • $|x| \geq 0$ for all $x$
  • $|x \cdot y| = |x| \cdot |y|$
  • $|x + y| \leq |x| + |y|$ (triangle inequality)
  • $|-x| = |x|$

Timing

The Xilinx Floating Point IP has zero latency for absolute value:

Property Latency (clock cycles)
Absolute Value 0

The output is combinationally derived from the input (sign bit is cleared). However, the AXI-Stream handshake may introduce pipeline delays.

Typical use cases

  • Signal magnitude extraction
  • Distance calculations
  • Error magnitude computation
  • Complex number magnitude (with additional operations)
  • Rectification in signal processing

Waveform example

Example with TM Factor = 4, Single precision.

Note: Zero latency - output available immediately (combinational).