TM
Block Preview

Introduction

This block performs parallel equality comparisons on time-multiplexed (TM) data streams. Each TM phase is compared independently, producing a TM boolean output:

$$ \mathrm{OUT_TM}[i] = \begin{cases} 1 & \text{if } \mathrm{IN1}[i] = \mathrm{IN2}[i] \ 0 & \text{otherwise} \end{cases} $$

for each TM phase $i = 0$ to $N-1$ where $N$ is the TM Factor.

The component supports two input modes:

  • IN2 Mode = TM: Both inputs are time-multiplexed (phase-by-phase comparison)
  • IN2 Mode = STD: IN2 is a single value compared against all IN1 phases

Pin Description

IN1 Input Variable (TM) bit TM
First TM input stream. Width: Input bits × TM Factor Always TM: Contains N packed samples.
Default: Must be connected
IN2 Input Variable bit TM
Second input (TM or STD depending on IN2 Mode). TM Mode: Width = Input bits × TM Factor (N packed samples) STD Mode: Width = Input bits (single value)
Default: Must be connected
OUT_TM Output Variable (TM) bit TM
TM boolean output (comparison results for all phases). Width: TM Factor bits (one bit per phase) Bit[i] = ‘1’ when IN1[i] equals IN2[i] (or IN2 if STD mode).
OUT Output 1 bit BIT
Collapsed single-bit output (OR reduction of OUT_TM). ‘1’ if ANY phase has equal inputs, ‘0’ if all phases differ. Width: 1 bit
CLK 1 bit
Clock input (only present when RegisterOutput = Enable). Used to register the comparison results.

Properties

Property window

Input bits InputSize

Set the number of bits of the input (per TM phase)

Number of bits per input sample (per TM phase). Range: 2-2048 bits. Applies to each slice of the TM data.

Default: 16

Range: 2 – 2048

Input sign InputSign

Select the sign/unsign of the input

Selects input interpretation: UNSIGNED (default) or SIGNED (two’s complement). For equality, this does not affect the result.

Default: UNSIGNED

Options: UNSIGNED SIGNED

TM Factor TMFactor

Select the TM Factor of the input

Time-multiplexing factor (number of parallel phases). Allowed values: 2, 4, 8, 16, 32. Higher values increase throughput but consume more resources.

Default: 4

Options: 2 4 8 16 32

IN2 Mode IN2_Mode

Select if IN2 is Time-Multiplexed or a single STD signal

Input mode for IN2: TM (time-multiplexed, phase-matched comparison) or STD (single value compared against all IN1 phases).

Default: TM

Options: TM STD

RegisterOutput EnableRegister

Enable one pipeline stage adding a register

Adds output register stage. Disable (combinational, zero latency) or Enable (registered, 1 clock cycle latency).

Default: Disable

Options: Disable Enable

Functional description

The Equal [TM] comparator replicates the standard Equal comparator N times in parallel, where N is the TM Factor. This enables efficient comparison of multiple data pairs per clock cycle.

TM-to-TM Comparison (IN2 Mode = TM)

When both inputs are TM: $$ \mathrm{OUT_TM}[i] = (\mathrm{IN1}[i] == \mathrm{IN2}[i]) \quad \text{for } i = 0 \ldots N-1 $$

Each phase is compared independently.

TM-to-STD Comparison (IN2 Mode = STD)

When IN2 is a standard (non-TM) signal: $$ \mathrm{OUT_TM}[i] = (\mathrm{IN1}[i] == \mathrm{IN2}) \quad \text{for } i = 0 \ldots N-1 $$

The single IN2 value is compared against all phases of IN1.

Time Multiplexing

Time multiplexing (TM) packs multiple data samples into a wider bus:

IN1 structure (TM Factor = 4, Input bits = 16):

  IN1[63:0] = [Phase3][Phase2][Phase1][Phase0]
            [15:0]  [31:16] [47:32] [63:48]

Each 16-bit slice represents one sample in the TM stream.

Output Formats

The component provides two output pins:

  1. OUT_TM: TM boolean output (N bits, one per phase)
  2. OUT: Collapsed single-bit output (OR reduction of OUT_TM)

Latency and Timing

RegisterOutput Latency (clock cycles)
Disable 0
Enable 1

All TM phases are processed in parallel within the same clock cycle.

Typical use cases

  • High-throughput comparison in parallel data processing
  • Multi-channel signal comparison
  • Parallel pattern matching
  • Vector equality checking