Xilinx
Block Preview

Introduction

The block converts fixed-point integer values to IEEE-754 floating-point format, enabling seamless integration between integer and floating-point arithmetic domains. On every rising edge of CLK, if CE = 1, the converter performs

$$ \mathrm{F}(n) = \text{float}(\mathrm{A}(n)), $$

where the input A is a custom fixed-point format with user-defined integer and fractional bit widths, and the output F follows IEEE-754 single or double precision.

The conversion is implemented with the Xilinx floating_point IP core configured for Fixed_to_float operation with blocking flow control and a fixed 7-cycle latency.

Pin Description

A Input Variable bit BIT VECTOR
Fixed-point input value. Width: Integer part n-bit + Fractional part n-bit (configurable 0-64 each). Interpreted as signed integer with configurable fractional scaling.
Default: Must be connected
CE Input 1 bit BIT
Clock Enable (tvalid), active high. When CE = 1, input A is accepted and conversion begins. Can be tied to ‘1’ for continuous operation.
Default: 1
READY_IN Input 1 bit BIT
Downstream ready signal (tready input), active high. Indicates if downstream logic can accept new data. Can be tied to ‘1’ if backpressure is not needed.
CLK Input 1 bit BIT
Global clock. Every rising edge triggers pipeline advancement. Connected to system acquisition clock.
Default: Default Board Clock
F Output 32 bit BIT VECTOR
Floating-point output value (IEEE-754). Width: 32 bits (Single) or 64 bits (Double). Valid when DV = 1.
DV Output 1 bit BIT
Data Valid output (tvalid), active high. Indicates when output F contains valid converted data. Asserts 7 clock cycles after corresponding CE = 1.
READY_OUT Output 1 bit BIT
Upstream ready signal (tready output), active high. Indicates this block can accept new input data. Used for flow control in streaming pipelines.

Properties

Property window

Integer part n-bit IntLength

Number of bits in the integer part of the input

Number of bits in the integer part of the fixed-point input. Range: 0 - 64. Determines the maximum integer magnitude that can be represented. Total input width = IntLength + FractLength.

Default: 32

Range: 0 – 64

Fractional part n-bit FractLength

Number of bits in the factional part of the input

Number of bits in the fractional part of the fixed-point input. Range: 0 - 64. Determines the precision of fractional values. The input value is interpreted as $A / 2^{\text{FractLength}}$.

Default: 0

Range: 0 – 64

Float Format FloatFormat

Select between single precision 32 bit and double precision 64 bit

Output floating-point precision:

  • Single → 32-bit (8-bit exponent, 24-bit mantissa including implicit bit)
  • Double → 64-bit (11-bit exponent, 53-bit mantissa including implicit bit)

Single precision provides ~7 decimal digits; Double provides ~16 decimal digits.

Default: Single

Options: Single Double

Functional description

The component converts fixed-point input to floating-point output:

$$ F = \text{float}\left(\frac{A}{2^{F_{\text{bits}}}}\right), $$

where:

  • A → input fixed-point value (signed integer)
  • F → output floating-point value (IEEE-754)
  • $F_{\text{bits}}$ → Fractional part n-bit property

The total input width is Integer part n-bit + Fractional part n-bit, allowing representation of values from very large integers to small fractional numbers.

IEEE-754 Format

The output follows standard IEEE-754 encoding:

Single precision (32-bit):

  • 1 sign bit
  • 8 exponent bits
  • 23 mantissa bits (24 with implicit leading 1)

Double precision (64-bit):

  • 1 sign bit
  • 11 exponent bits
  • 52 mantissa bits (53 with implicit leading 1)

Timing

The IP has a fixed 7-cycle pipeline latency:

Clock cycle Event
0 Input A presented with CE = 1
7 Output F valid with DV = 1

The READY_IN/READY_OUT handshake signals enable backpressure control for streaming applications.

Typical use cases

  • Converting ADC integer samples to floating-point for DSP processing
  • Interface between fixed-point arithmetic front-ends and floating-point algorithms
  • Preprocessing for scientific computations requiring high dynamic range
  • Data type conversion in mixed-precision pipelines