TM
Block Preview

Introduction

This block performs an arithmetic right shift operation on time-multiplexed (TM) data streams. Each bit of the input is shifted right by the specified Shift amount, and copies of the sign bit (MSB) are inserted in the vacant leftmost positions.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT}(n) = \mathrm{IN}(n) \gg_{\text{arith}} S, $$

where $S$ is the Shift parameter. The TM Factor property determines how many parallel samples are processed per clock cycle.

Unlike logical right shift, this arithmetic shift preserves the sign bit (MSB), making it suitable for signed two’s complement arithmetic.

Pin Description

IN Input Variable bit TM
Input binary data (two’s complement signed), always TM. Width: Input Width × TM Factor Each TM phase receives its corresponding slice of the input bus.
Default: Must be connected
OUT Output 16 bit TM

Arithmetic right-shifted output (signed), always TM (same factor as IN). Width: Output Size × TM Factor

  • Output Size = Input Width (SAME SIZE mode)
  • Output Size = Input Width - Shift (SHIFTED SIZE mode)

Output is combinational (zero latency). Sign bit is preserved in all output bits.

Properties

Property window

Input Width (per phase) InputWidth

Set the input word size in bits per phase

Number of bits per input sample ($N_\text{in}$). Range: 2 – 128. Each TM phase processes samples of this width. The MSB is treated as the sign bit.

Default: 16

Range: 2 – 128

TM Factor TMFactor

Set the time multiplexing factor (number of phases)

Time-multiplexing factor (number of parallel phases). Allowed values: 2, 4, 8, 16, 32 (up to 32). Higher values increase throughput proportionally but consume more FPGA resources (one shift instance per TM phase).

Default: 4

Range: 2 – 32

Shift Shift

Number of bits to be shifted

Number of bit positions to shift right ($S$). Range: 0 – 127. When Shift = 0, output equals input (no operation). When Shift ≥ Input Width, output is all sign bits (all 0s or all 1s).

Default: 1

Range: 0 – 127

Output Size OutputSize

Select if output should have same size of input or should be INPUT_SIZE-SHIFT

Output bit width mode:

  • SAME SIZE → Output width = Input width (standard mode)
  • SHIFTED SIZE → Output width = Input width - Shift (truncated to remaining bits)

Choose SAME SIZE for standard signed shift operations. Choose SHIFTED SIZE when only the remaining bits are needed (reduced width).

Default: SAME SIZE

Options: SAME SIZE SHIFTED SIZE

Functional description

The component implements a bitwise arithmetic right shift in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.

For each TM phase, the operation is:

$$ y[i] = x[i] \gg_{\text{arith}} S, $$

where:

  • $x[i]$ → input sample at phase $i$
  • $y[i]$ → output sample at phase $i$
  • $S$ → shift amount (constant across all phases)

The arithmetic right shift operation shifts bits right and replicates the MSB (sign bit):

$$ y = \text{sign_extend}(\lfloor x / 2^S \rfloor) $$

Output size modes

The block offers two output width configurations:

  • SAME SIZE: Output width = Input width The output is the same size as input; shifted bits are preserved.

  • SHIFTED SIZE: Output width = Input width - Shift amount Only the remaining bits after the shift are output (truncated to smaller width).

Example with positive value

Given an 8-bit input 01010110 (+86 in two’s complement) and shift amount = 2:

  • Arithmetic shift result: 00010101 (+21)
  • SAME SIZE (8 bits): 00010101
  • SHIFTED SIZE (6 bits): 010101

Example with negative value

Given an 8-bit input 11010110 (-42 in two’s complement) and shift amount = 2:

  • Arithmetic shift result: 11110101 (-11, sign preserved)
  • SAME SIZE (8 bits): 11110101
  • SHIFTED SIZE (6 bits): 110101

Comparison with logical shift

  • Arithmetic right shift: Fills with sign bit (MSB) → signed division by 2^S
  • Logical right shift: Fills with zeros → unsigned division by 2^S

Example with negative 8-bit number 11010110 (-42 in two’s complement), shift = 2:

  • Arithmetic: 11110101 (-11, preserves sign, correct signed division)
  • Logical: 00110101 (+53, loses sign information)

Mathematical background

Arithmetic right shift by $S$ positions is equivalent to signed integer division by $2^S$ with rounding toward negative infinity:

$$ x \gg_{\text{arith}} S = \lfloor x / 2^S \rfloor \quad \text{(for two’s complement)} $$

This is commonly used for:

  • Fast signed division by powers of 2
  • Scaling signed fixed-point values
  • Implementing signed arithmetic in DSP algorithms
  • Maintaining sign in signal processing operations

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Right Shift Signed TM 0

All TM phases are processed in parallel within the same clock cycle.

Typical use cases

  • Fast signed division by powers of 2 in DSP
  • Signed fixed-point arithmetic rescaling
  • Audio/video signal processing with signed samples
  • Building blocks for signed ALUs and arithmetic units
  • Two’s complement number manipulation

Waveform example

Example with TM Factor = 4, Shift = 2, Input = signed values (4-bit two’s complement), SAME SIZE mode.

Note: Output is available immediately (combinational logic). Values in hex (4-bit): 0x6 (+6) » 2 = 0x1 (+1), 0xE (-2) » 2 = 0xF (-1, sign preserved), 0xA (-6) » 2 = 0xE (-2), 0x3 (+3) » 2 = 0x0 (0).