Xilinx
TM
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Introduction

TM version of the FFT Filter: the stream (R samples/clock) is filtered by fast convolution with 50% overlap-save. Engine A transforms frames $[jN, jN+N)$; engine B receives the input delayed by $N/2$ samples and covers the interleaved frames. Each engine is a full polyphase chain: gapless forward FFT (as FFT TM Realtime, No Scaling) -> per-lane complex multiply by $H[k]$ (Q15, lane $q$ holds bins $k + qN/R$) -> gapless inverse FFT (as IFFT TM Realtime, Scale). The valid second half of every reconstructed frame is kept; engine A is re-timed by $N/2R$ clocks (half a polyphase frame, the same depth as engine B’s input delay line) so the halves tile exactly: continuous, ordered TM output with DV always high.

Double-clicking opens the shared FFT Filter designer (LP/HP/BP/BS presets, response drawn by editable points, coefficients from file, H[k] CSV export). H must be conjugate-symmetric for a real output - automatic with the designer.

Pin Description

DATA_IN Input 16 bit TM
TM input, R x 16 bit.
Default: Must be connected
CLK Input 1 bit BIT
TM-domain clock.
Default: Default Board Clock
DATA_OUT Output 16 bit TM
Filtered TM stream, R x 16 bit.
DV Output 1 bit BIT
High continuously once the pipeline is filled.

Properties

Property window

FFT Length Length

FFT block size N (power of 2). Filter impulse response up to N/2 taps.

FFT block size N (256..16384). Filter length up to N/2 taps.

Default: 1024

Options: 256 512 1024 2048 4096 8192 16384

TM Factor (SSR) TMFactor

Time Multiplexing factor (samples per clock). 2 or 4.

TM factor R: 2 or 4.

Default: 4

Options: 2 4

Filter Filter

Filter summary (set by the designer, double-click)

Summary of the designed filter (set by the designer).

Default: Passthrough

Config (JSON, use designer) FFProject

Designer state incl. H[k] Q15 coefficients

Cost and constraints

  • $4R$ xfft cores of $N/R$ points (2 fwd + 2 inv polyphase engines) plus $2R$ complex multipliers: this is the price of full rate on a TM stream. For R=4, N=1024: 16 xfft of 256 points.
  • Impulse response up to N/2 taps; latency ~3 N/R clocks.
  • TM factor 2 or 4; input/output 16 bit.

Runtime coefficients : FFT Filter TM Prog

H[k] in RAM, loaded via COEF_ADDR / COEF_DATA / COEF_WE: addresses 0..N-1 = RE, N..2N-1 = IM (Q15, passthrough until loaded) - the same address map produced by the designer CSV export. Load while idle.