Petiroc Frame Transfer

Introduction link

Principle of Operation link

A DT5550W carries four PETIROC-2A chips, each read out by its own Petiroc Digital block. Those four blocks produce events asynchronously. This block merges them into one ordered stream and gives the host a single FIFO to read.

   Petiroc Digital A ──► DATA_A / TS_T0_A / TS_A / DV_A ──┐
 Petiroc Digital B ──► …                                 │   ┌──────────┐
 Petiroc Digital C ──► …                                 ├──►│ arbiter  │
 Petiroc Digital D ──► …                                 │   │ A→B→C→D  │
                                                         ┘   └────┬─────┘
                                                                  │ 38 words
                                                            ┌─────▼──────┐
                                                            │ async FIFO │──► host
                                                            │  memLength │
                                                            └────────────┘
  

The arbiter visits one input per clock cycle (A, B, C, D, A, …). When the visited input has DV high and is not disabled in the control register, the whole frame is assembled in a 38 × 32-bit latch in a single clock, the input is acknowledged, and the frame is then streamed into the FIFO one word per clock for the next 38 clocks.

The frame link

Every event is exactly 38 words of 32 bits:

The host resynchronises on the header (word >> 4 == 0x8000000) and validates on the trailer (word & 0xC0000000 == 0xC0000000); a frame whose trailer does not match is discarded and the decoder goes back to hunting for a header.

Pin Description link

Properties link

⚙️ Detailed Operation link

Payload layout - the authoritative field map link

Words 5…36 are the raw bit stream the ASIC sent, packed by Petiroc Digital as "00" & <30 ASIC bits> per word. The host decoder re-cuts each of those 32 words into three 10-bit fields:

  datarow[j*3 + 0] = (word >> 20) & 0x3FF;   /* first  10 bits received */
datarow[j*3 + 1] = (word >> 10) & 0x3FF;
datarow[j*3 + 2] = (word >>  0) & 0x3FF;   /* last   10 bits received */
  

for j = 0 … 31, giving 96 fields (32 words × 30 bits ÷ 10). Those 96 fields map onto the 32 channels as:

i.e. the first 64 fields are per-channel (fine time, charge) pairs interleaved, and the last 32 fields carry one hit bit each. All 10-bit values are Gray coded - the decoder calls gray_to_bin(value, 10) on every one of them. If you decode the frame yourself, the Gray conversion is not optional.

   word 5        word 6        …        word 36
┌──────────┐  ┌──────────┐           ┌──────────┐
│00│f0│q0│f1│ │00│q1│f2│q2│    …     │00│h29│h30│h31│
└──────────┘  └──────────┘           └──────────┘
   f = fine time (gray10)   q = charge (gray10)   h = hit (bit 0 of a 10-bit field)
  

Arbitration and event loss link

The arbiter advances ARBITERID every clock, so the four inputs are polled in a fixed A → B → C → D rotation. Writing a frame occupies the FIFO port for 38 clocks, during which no other input is polled - the worst-case service latency for an input that raises DV just after its slot is 3 + 38 = 41 clock cycles.

Control and status registers link

CompileMMC declares a FIFO-read endpoint with two registers, CONTROL (W) and STATUS (R), plus the FIFO address itself.

CONTROL (write only):

Bit 8 is level sensitive and sits outside the clocked branch, so writing 0x100 holds the block in reset until something else is written. That is exactly what the generated start-up pair does:

  PETIROCFRAME_<name>_RESET(&handle);   /* writes 0x100 -> flush + hold */
PETIROCFRAME_<name>_START(&handle);   /* writes 0x000 -> release      */
  

STATUS (read only):

read back by PETIROCFRAME_<name>_GetStatus(&is_data_available, &word_available, &handle) as temp & 0x01 and (temp >> 16) & 0xFFFF.

The FIFO link

An xpm_fifo_async of memLength 32-bit words (the Samples property), read latency 1, standard (non-FWFT) read mode, 2 CDC stages. Both its write and read clocks are wired to the project’s global clock by CompileHDL, so in a stock design it behaves as a synchronous FIFO; the asynchronous primitive is there so the host-side read port can be moved to another clock.

Thresholds are chosen in units of one frame:

• PROG_FULL_THRESH = memLength - 38 → FULL asserts when there is less than one frame of room left, which is what makes the dropped-frame case above the only failure mode instead of a torn frame.
• PROG_EMPTY_THRESH = 38 → DATA_AVAL and STATUS(0) assert only when at least one complete frame is present, so a host that reads 38 words when the flag is set always gets a whole event.

Event capacity is floor(memLength / 38): 215 events at the default 8192 words.

Host read sequence link

  void *buf = NULL;
Utility_ALLOCATE_DOWNLOAD_BUFFER(&buf, 1024*1024);
PETIROCFRAME_PetirocFrame0_RESET(&handle);
PETIROCFRAME_PetirocFrame0_START(&handle);

while (1) {
    uint32_t avail = 0, words = 0;
    PETIROCFRAME_PetirocFrame0_GetStatus(&avail, &words, &handle);
    if (!avail) continue;

    PETIROCFRAME_PetirocFrame0_DOWNLOAD(data_frame, N_Packet * 38,
                                        timeout_ms, &handle,
                                        &read_data, &valid_data);
    Utility_ENQUEUE_DATA_IN_DOWNLOAD_BUFFER(buf, data_frame, valid_data, &enqueued);
    PETIROCFRAME_PetirocFrame0_RECONSTRUCT_DATA(buf, &decoded_packets);

    for (int i = 0; i < decoded_packets.valid_packets; i++)
        /* .Pack_Id .Time_Code .RunTime_Code .AsicID
           .Charge[32] .Hit[32] .FineTime[32] */ ;

    free_PETIROCFRAME_packet_collection(&decoded_packets);
}
  

The decoder is stream oriented: it is fed from a circular buffer, so a download that cuts a frame in half is recovered on the next call. It returns -1 if the buffer holds less than one frame and -2 if it cannot allocate the output arrays.

The Python library generated alongside offers PETIROCFRAME_<name>_RESET/_START/_GET_STATUS/_GET_DATA/_RECONSTRUCT_DATA, the last returning AsicId, Time_Code, RunTime_Code, Pack_Id, Charge, Hit, Fine, Coarse.

Wiring note link

Unused ASIC inputs may be left open; their DV_x then reads as the pad default and the corresponding control bit can be set to 1 to make the mask explicit. ACK_x must go back to the DV_ACK pin of the matching Petiroc Digital block, otherwise DV is never cleared and the same event is re-latched on every rotation.

Resources & Timing link

• Latency: Up to 3 clocks of arbitration plus 38 clocks to stream one frame into the FIFO; worst case 41 clocks from DV to the last word written.

• Throughput: One frame per 38 clocks, i.e. up to ≈ 4.2 Mevents/s at 160 MHz, far above what a PETIROC-2A readout can produce. The real limit is the host link.

• Frame size is fixed at 38 words of 32 bits (152 bytes) regardless of how many channels actually fired.
• The packet counter in word 4 is shared by all four ASICs, so it orders events across chips and its gaps reveal drops.
• The entity has a reset port, but the architecture never reads it: the block is reset only by the framework’s FIFO reset net or by CONTROL bit 8.