ALU - FX GAIN
Fixed-point gain (multiplication) block implemented via Vivado HLS. Supports independent configuration of integer and fractional widths for input, gain, and output with automatic rounding and saturation. Optimized for high-speed DSP applications.
Introduction
The FX GAIN block performs fixed-point multiplication between a data input and a gain coefficient:
$$ \mathrm{OUT} = \mathrm{IN} \times \mathrm{GAIN} $$
Each operand (input, gain, output) has independently configurable integer and fractional bit widths, allowing precise control over dynamic range and precision. The block uses Xilinx HLS for hardware generation, providing optimal resource utilization.
Output includes automatic rounding (AP_RND) and saturation (AP_SAT_SYM) to handle overflow conditions gracefully.
Pin Description
IN.
IN_DV.
Properties
Number of bits of the integer part of the input
Number of integer bits for inputIN.
Range: 0 – 128.
Determines integer dynamic range: [$-2^{N-1}$, $2^{N-1}-1$] (signed).
Default: 16
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Number of bits of the fractional part of the input
Number of fractional bits for inputIN.
Range: 0 – 128.
Determines fractional precision: LSB = $2^{-N}$.
Default: 0
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Select if the input is signed or unsigned. Sign uses 1 bit of the integer part
Input arithmetic type:
- UNSIGNED: ap_ufixed, range [0, $2^{N}-1$]
- SIGNED: ap_fixed, range [$-2^{N-1}$, $2^{N-1}-1$]
Default: UNSIGNED
Options: UNSIGNED SIGNED
Number of bits of the integer part of the output
Number of integer bits for outputOUT.
Range: 0 – 128.
Should accommodate IN_int + GAIN_int to avoid saturation.
Default: 16
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Number of bits of the fractional part of the output
Number of fractional bits for outputOUT.
Range: 0 – 128.
Determines output precision after rounding.
Default: 0
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Select if the output is signed or unsigned. Sign uses 1 bit of the integer part
Default: UNSIGNED
Options: UNSIGNED SIGNED
Number of bits of the integer part of the gain
Number of integer bits for gain coefficient. Range: 0 – 128. Default: 2 (allows gains up to 2.0 for unsigned).Default: 2
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Number of bits of the fractional part of the gain
Number of fractional bits for gain coefficient. Range: 0 – 128. Default: 14 (precision ~ 0.00006).Default: 14
Options: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
Select if the gain is signed or unsigned. Sign uses 1 bit of the integer part
Default: UNSIGNED
Options: UNSIGNED SIGNED
Gain arithmetic type:
- UNSIGNED: Non-negative gains only
- SIGNED: Allows negative gains (signal inversion)
Output arithmetic type:
- UNSIGNED: ap_ufixed
- SIGNED: ap_fixed (required if input or gain is signed)
Functional description
The component multiplies two fixed-point numbers with configurable formats:
$$ y = x \times g $$
where:
x→INwith format $(N_{\text{int}}, N_{\text{frac}})$g→GAINwith format $(G_{\text{int}}, G_{\text{frac}})$y→OUTwith format $(O_{\text{int}}, O_{\text{frac}})$
Fixed-point format
Each signal uses the ap_fixed/ap_ufixed HLS types:
- Total width = Integer bits + Fractional bits
- Signed/Unsigned configured independently per signal
- Rounding mode: AP_RND (round to nearest)
- Overflow mode: AP_SAT_SYM (symmetric saturation)
Data flow
The block uses a data-valid protocol:
IN_DV: Input data valid signalOUT_DV: Output data valid signal (delayed by latency)
Latency
Fixed latency of 6 clock cycles (HLS-optimized pipeline).
Typical use cases
- Signal scaling and calibration
- Adjustable gain amplifiers
- Channel equalization
- Amplitude modulation in SDR