TM
Block Preview

Introduction

This block performs a bitwise NOT (inversion) operation on time-multiplexed (TM) data streams. Each bit of the input is inverted: 0 becomes 1, and 1 becomes 0.

The operation is purely combinational with zero clock latency:

$$ \mathrm{OUT}(n) = \lnot \mathrm{IN}(n), $$

where $\lnot$ represents the logical NOT operation. The TM Factor property determines how many parallel samples are processed per clock cycle.

Pin Description

IN_0 Input 16 bit TM
OUT Output 16 bit TM

Inverted output, always TM (same factor as IN). Width: Input Size × TM Factor

Output is combinational (zero latency).

IN Variable bit
Input data, always TM. Width: Input Size × TM Factor Each TM phase receives its corresponding slice of the input bus.
Default: Must be connected

Properties

Property window

Input size (bits) InputSize

Set the size of each input in bits

Number of bits per input sample. Range: 1 – 16384. Each TM phase processes samples of this width.

Default: 16

Range: 1 – 16384

TM Factor TMFactor

Time Multiplexing factor (number of phases)

Time-multiplexing factor (number of parallel phases). Allowed values: 2 – 32. Higher values increase throughput proportionally but consume more FPGA resources.

Default: 4

Range: 2 – 32

Functional description

The component implements a bitwise NOT gate in VHDL, replicated N times (where N = TM Factor) to support time-multiplexed data streams.

For each TM phase and each bit position:

$$ y[i] = \lnot x[i], $$

where:

  • $x[i]$ → input bit $i$
  • $y[i]$ → output bit $i$
  • $\lnot$ → logical NOT operation

The NOT gate is the fundamental inversion operation in digital logic. Truth table:

IN OUT
0 1
1 0

Applications

  • Bitwise inversion for signal polarity reversal
  • Creating active-low signals from active-high (or vice versa)
  • Building blocks for XOR and other logic gates
  • Bit masking and complement generation

Mathematical background

The NOT operation is the logical negation in Boolean algebra:

$$ \lnot 0 = 1, \quad \lnot 1 = 0 $$

For multi-bit vectors, NOT is applied bit-wise:

$$ \lnot(b_{n-1} b_{n-2} \ldots b_1 b_0) = (\lnot b_{n-1})(\lnot b_{n-2}) \ldots (\lnot b_1)(\lnot b_0) $$

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Logic NOT TM 0

All TM phases are processed in parallel within the same clock cycle.

Typical use cases

  • Signal polarity inversion in trigger logic
  • Creating complementary signals
  • Bitwise masking operations
  • Building complex logic functions