Block Preview

Introduction

The block performs addition of two input streams on every rising edge of CLK. When CE = 1, the adder performs

$$ \mathrm{OUT}(n) ;=; \mathrm{IN1}(n) + \mathrm{IN2}(n), $$

where the arithmetic is signed or unsigned according to the Input sign 1 and Input sign 2 properties. A synchronous active-high RESET clears the internal pipeline to zero. The internal datapath is implemented with the Xilinx c_addsub IP core; the Latency property lets you trade off clock frequency versus latency by inserting 1, 2, 4 or 8 pipeline stages.

Pin Description

IN1 Input Variable bit BIT VECTOR
First integer input operand. Width: Input bits 1 (2 – 256). Arithmetic type is set by Input sign 1.
Default: Must be connected
IN2 Input Variable bit BIT VECTOR
Second integer input operand. Width: Input bits 2 (2 – 256). Arithmetic type is set by Input sign 2.
Default: Must be connected
CLK Input 1 bit BIT
Global clock. Every rising edge triggers a new addition cycle and propagates pipeline registers.
Default: Default Board Clock
CE Input 1 bit BIT
Clock Enable, active high. When CE = 0 the adder holds its current value; pipeline registers keep their previous state.
Default: 1
RESET Input 1 bit BIT
Synchronous reset, active high. Forces all pipeline stages to zero on the next rising clock edge.
Default: Default Board Reset
OUT Output 32 bit BIT VECTOR
Sum of the input samples: OUT = IN1 + IN2. Width: Output Size (2 – 256). Valid data appear after Latency clock cycles.

Properties

Property window

Input bits 1 InputSizeA

Set the number of bits of the input

Number of bits of IN1 ($N_{\text{in1}}$). Range 2 – 256. Changing this value re-configures the underlying c_addsub core and may update synthesis results.

Default: 32

Range: 2 – 256

Input bits 2 InputSizeB

Set the number of bits of the input

Number of bits of IN2 ($N_{\text{in2}}$). Range 2 – 256. Changing this value re-configures the underlying c_addsub core and may update synthesis results.

Default: 32

Range: 2 – 256

Output Size OutputSize

Set the number of bits of the output

Width of the output register OUT ($N_\text{out}$). Range 2 – 256. Must be ≥ max(Input bits 1, Input bits 2) to avoid truncation. Internally mapped to C_OUT_WIDTH.

Default: 32

Range: 2 – 256

Input sign 1 InputSignA

Select the sign/unsign of the input

Selects arithmetic type of IN1:

  • UNSIGNED → non-negative integers, wrap-around at $2^{N}-1$.
  • SIGNED → two’s-complement, range $[-2^{N-1},,2^{N-1}-1]$.

Default: UNSIGNED

Options: UNSIGNED SIGNED

Input sign 2 InputSignB

Select the sign/unsign of the input

Selects arithmetic type of IN2:

  • UNSIGNED → non-negative integers, wrap-around at $2^{N}-1$.
  • SIGNED → two’s-complement, range $[-2^{N-1},,2^{N-1}-1]$.

Default: UNSIGNED

Options: UNSIGNED SIGNED

Latency Latency

Number of pipeline stages

Number of pipeline stages inserted into the adder datapath. Allowed values: 1, 2, 4, 8. Directly mapped to C_LATENCY / Latency parameters, hence Total delay = Latency × T_CLK. Higher values increase maximum clock frequency at the cost of latency.

Default: 4

Options: 1 2 4 8

Functional description

The component realizes a pipelined two-input adder:

$$ y[n] = x_1[n] + x_2[n], $$

with

  • x_1[n] → IN1
  • x_2[n] → IN2
  • y[n] → OUT

Both input and output widths are user-selectable. If Output Size > max(Input bits 1, Input bits 2) the adder offers additional head-room, reducing the probability of wrap-around. Arithmetic overflow follows the native behaviour of VHDL signed/unsigned types (modulo $2^{\text{width}}$).

Mathematical background

In fixed-point hardware, the output is bounded by:

$$ y_\text{max} = 2^{N_\text{out}-1}-1 \quad(\text{signed}),\qquad y_\text{max} = 2^{N_\text{out}}-1 \quad(\text{unsigned}) $$

where $N_\text{out}$ is the Output Size.

Timing

The IP inserts a Latency-dependent pipeline:

Latency property Internal stages Total clock cycles from inputs to OUT
1 1 1
2 2 2
4 4 4
8 8 8

Therefore the deterministic delay is T_delay = Latency × T_CLK.

Typical use cases

  • Digital signal processing pipelines
  • Complex number arithmetic (real/imaginary parts)
  • Multi-channel data combination in SDR front-ends
  • Generic DSP pipelines requiring high-speed addition

Waveform example

Example with pipeline delay set to 4.