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Introduction

See the FFT Filter guide for the datapath, operation (full rate up to CE duty 100%, latency ~2.5 N) and design notes. This variant starts as a passthrough (H = 1) and takes its complex Q15 response at runtime: write RE[k] at address k and IM[k] at address N+k (address bit log2(N) selects the part), one COEF_WE pulse per value. Load while the input is idle. The FFT Filter designer CSV export produces exactly this address map.

Pin Description

DATA_IN Input 16 bit BIT VECTOR
16-bit signed input stream, CE gated.
Default: Must be connected
CE Input 1 bit BIT
Clock enable, any duty up to 100%. Default ‘1’.
Default: 1
COEF_ADDR Input 11 bit BIT VECTOR
Coefficient address: 0..N-1 = RE, N..2N-1 = IM.
COEF_DATA Input 16 bit BIT VECTOR
Coefficient value, signed Q15 (32767 = 1.0).
COEF_WE Input 1 bit BIT
Write strobe.
CLK Input 1 bit BIT
Clock.
Default: Default Board Clock
DATA_OUT Output 16 bit BIT VECTOR
Filtered 16-bit stream.
DV Output 1 bit BIT
Output sample valid.
BUSY Output 1 bit BIT
Frame in progress.
OVERRUN Output 1 bit BIT
Missed frame boundary.

Properties

Property window

FFT Length Length

FFT block size N (power of 2). H[k] loaded via COEF bus: addr bit log2(N) selects RE(0)/IM(1), data Q15.

FFT block size N (256..16384).

Default: 1024

Options: 256 512 1024 2048 4096 8192 16384