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Introduction

This block converts a VHDL INTEGER type signal to a std_logic_vector binary representation. It allows you to interface between VHDL’s high-level INTEGER type and the bit-level std_logic_vector type commonly used in digital design.

The operation is purely combinational with zero clock latency:

$$ \mathrm{BIN} = \mathrm{INT}[N-1:0], $$

where $N$ is the Output bits parameter (2 to 32 bits). The output can be configured as either SIGNED or UNSIGNED representation.

Pin Description

INT Input 1 bit INT
Input INTEGER signal. Type: VHDL INTEGER (32-bit signed) Range: -2,147,483,648 to 2,147,483,647
Default: Must be connected
BIN Output Variable bit BIT VECTOR

Output binary vector, always std_logic_vector. Width: Configurable via Output bits property (2 to 32 bits) Interpretation: Configurable via Output sign property

Output is combinational (zero latency).

Properties

Property window

Output bits OutputSize

Set the number of bits of the binary output

Number of bits in the binary output vector (2 to 32 bits). For full INTEGER range preservation, use 32 bits.

Default: 32

Range: 2 – 32

Output sign OutputSign

Select the sign/unsign of the binary output

Interpretation of the output binary vector: UNSIGNED (0 to 2^N-1) or SIGNED (two’s complement, -2^(N-1) to 2^(N-1)-1).

Default: UNSIGNED

Options: UNSIGNED SIGNED

Functional description

The component performs a direct type conversion from VHDL’s INTEGER type to std_logic_vector. In VHDL, the INTEGER type is defined as a 32-bit signed integer with range -2,147,483,648 to 2,147,483,647.

Conversion process

The conversion extracts the lower $N$ bits from the INTEGER value:

$$ \mathrm{BIN}[N-1:0] = \mathrm{INT}[N-1:0] $$

where:

  • $N$ → Output bits (2 to 32)
  • INT → Input INTEGER value
  • BIN → Output binary vector

Signed vs Unsigned output

The Output sign property determines how the output should be interpreted:

  • UNSIGNED: Output represents values 0 to $2^N - 1$

    • Negative input integers will wrap around (two’s complement preserved)
    • Example: -1 becomes 0xFFFFFFFF (32 bits)

  • SIGNED: Output represents values $-2^{N-1}$ to $2^{N-1} - 1$

    • MSB is the sign bit
    • Two’s complement representation
    • Example: -1 becomes 0xFFFFFFFF (32 bits)

Range considerations

  • If the INTEGER value exceeds the output bit width range, truncation occurs
  • For $N < 32$ bits, only the lower $N$ bits are extracted
  • The sign bit (bit 31) is preserved in the MSB only if $N = 32$

Example conversions

For a 16-bit UNSIGNED output:

  • INT = 42 → BIN = 0x002A
  • INT = -1 → BIN = 0xFFFF (wraps to 65535)
  • INT = 256 → BIN = 0x0100

For an 8-bit SIGNED output:

  • INT = 42 → BIN = 0x2A
  • INT = -1 → BIN = 0xFF
  • INT = 127 → BIN = 0x7F
  • INT = -128 → BIN = 0x80
  • INT = 256 → BIN = 0x00 (truncated)

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Integer To Binary 0

Output is available immediately in the same clock cycle.

Typical use cases

  • Converting integer constants to binary vectors
  • Interfacing between arithmetic units and bit-level logic
  • Extracting bit fields from integer values
  • Type conversion for component interfacing