Dual Oscilloscope

Introduction link

Principle of Operation link

Let

• $f_s$ = input sampling frequency (raw sampling clock)
• $D = \text{CONFIG_DECIMATOR}$, $N = 2^D$ (decimation ratio)
• $x_k(i)$ = raw sample $k$ of analog channel i
• $y_m(i)$ = decimated output sample $m$ of channel i

When $D = 0$ there is no decimation and every raw sample is stored (subject to circular buffer length).
When $D > 0$ the core keeps one raw sample every $N$ input cycles:

$$ y_m(i) = x_{mN}(i) $$

Dual Packing link

The memory interface uses 32-bit words arranged as channel pairs:

• Digital Disabled:
  Word layout (bits 31:0):

    [15:0]  = Channel (2n)
  [31:16] = Channel (2n+1)
    

  → 2 × 16-bit samples.

• Digital Enabled:
  Each analog sample width becomes 14 bits to fit digital lines:

    [13:0]   = Channel (2n)   (A_low14)
  [27:14]  = Channel (2n+1) (B_low14)
  [31:28]  = D3 D2 D1 D0    (one bit each)
    

  (Total = 14 + 14 + 4 = 32 bits.)

Channels are logically labeled A0…A(N-1). The pairing is (A0,A1), (A2,A3), … in consecutive words.

Trigger Flow (Conceptual) link

1. ARM (CONFIG_ARM 0→1) arms the capture engine and clears internal counters.
2. Continuous Sampling writes into a circular buffer per channel pair.
3. Trigger Evaluation each cycle (external START, analog threshold, software, or digital line).
4. Trigger Latch stores the write pointer as trigger position (READ_POSITION).
5. Post-Trigger Collection continues until total programmed samples (Samples) are filled.
6. Ready: READ_STATUS = 1, acquisition halts (buffer frozen for readout).

Deterministic behaviour is ensured because trigger evaluation, write pointer updates and memory writes occur inside the same CLK_WRITE domain.

Pin Description link

Properties link

⚙️ Detailed Timing link

Event Sequence link

1. ARM (CONFIG_ARM 0→1) clears counters & arms.
2. Sampling: every clock (period $T_{\text{CLK}} = 1/f_s$) one raw sample per channel is eligible.
3. Decimation (if $D>0$): only samples where the free-running decimation counter = 0 are stored; others are skipped.
4. Trigger Evaluation: performed each clock on instantaneous raw data.
5. Trigger: when condition true → latch current buffer position.
6. Completion: after post-trigger region filled → data ready.

Delay Between Trigger and Stored Sample link

If trigger coincides with a stored (kept) sample (decimation counter = 0), that sample is associated with the trigger.
If trigger occurs on a discarded raw sample (decimation counter ≠ 0), the last stored sample before trigger represents the closest pre-trigger point. There is no averaging delay.

Latency pipeline (write path) = 2 clock cycles (register + RAM). Thus: $$ t_{\text{lat}} \approx 2T_{\text{CLK}} $$

Temporal distance between consecutive stored samples is: $$ \Delta t_{\text{stored}} = \begin{cases} T_{\text{CLK}} & D=0 \ N T_{\text{CLK}} & D>0 \end{cases} $$

Timing uncertainty (trigger to nearest stored sample) when $D>0$ is bounded by: $$ 0 \le \delta t < (N-1)T_{\text{CLK}} $$ because up to $N-1$ raw samples can be skipped after the last stored sample preceding the trigger.

Pre-Trigger Region link

CONFIG_PRETRIGGER = P (in stored output samples). Required history in time:

$$ T_{\text{pre}} = \begin{cases} \dfrac{P}{f_s} & D=0 \ \dfrac{PN}{f_s} & D>0 \end{cases} $$

Full pre-trigger is only available if the system stayed armed long enough before the trigger.

Post-Trigger Region link

With total stored samples $S = Samples$:

• Post-trigger samples = $S-P$
• Duration: $$ T_{\text{post}} = \begin{cases} \dfrac{S-P}{f_s} & D=0 \ \dfrac{(S-P)N}{f_s} & D>0 \end{cases} $$

Total span: $$ T_{\text{total}} = \begin{cases} \dfrac{S}{f_s} & D=0 \ \dfrac{SN}{f_s} & D>0 \end{cases} $$

Circular Buffer Reordering link

After download, reorder so the trigger sample appears at index $P$:

1. Read READ_POSITION = $I_T$ (index of trigger-associated stored sample).
2. Compute: $$ \text{fix_position} = I_T - P $$
3. If fix_position > 0:

     reordered = data[fix_position:] + data[:fix_position]
     

   Else:

     idx = fix_position + S
   reordered = data[idx:] + data[:idx]
     

Word Decoding (Software) link

Digital Disabled (16+16):

  sampleA = word & 0xFFFF;
sampleB = (word >> 16) & 0xFFFF;
  

Digital Enabled (14+14+4):

  sampleA =  word        & 0x3FFF;      // bits 13:0
sampleB = (word >> 14) & 0x3FFF;      // bits 27:14
d0 = (word >> 28) & 0x1;
d1 = (word >> 29) & 0x1;
d2 = (word >> 30) & 0x1;
d3 = (word >> 31) & 0x1;
  

Quick Reference link

Notes link

• Choose $P$ considering available buffer depth; early triggers can reduce effective pre-trigger history.
• When digital is enabled, software must scale 14-bit values (e.g. left-shift by 2) if a uniform 16-bit range is expected downstream.

Oscilloscope Configuration Registers link

CONFIG_ARM link

Rising edge (0→1) arms acquisition (write 0 then 1 to re-arm).

CONFIG_DECIMATOR link

Sets decimation exponent $D$ (0: no decimation; $N=2^D$). Implements sample skipping (no averaging).

CONFIG_TRIGGER_MODE link

Trigger configuration (source, edge, software trigger bit, channel selection), same bit allocation as original oscilloscope core:

CONFIG_PRETRIGGER link

Number $P$ of stored output samples to appear before the trigger after reordering.

CONFIG_TRIGGER_LEVEL link

Threshold (LSB) for analog comparator when analog trigger enabled.

READ_STATUS link

Acquisition status (0 = not ready, 1 = data ready).

READ_POSITION link

Index $I_T$ (in raw stored sample space) of the trigger-associated stored sample.

Reading Waveform Data link

When READ_STATUS = 1 read Samples * (channels/2) 32-bit words (each word holds two channel samples, plus optional digital bits). Reorder per above.