Block Preview

Introduction

This block implements combined gate and delay functionality, delaying an input pulse by a programmable number of clock cycles and holding the output HIGH for a programmable gate width.

When IN goes HIGH:

  • Output is delayed by DELAY clock cycles
  • Output stays HIGH for GATE clock cycles
  • Then returns LOW

Pin Description

IN Input 1 bit BIT
Input trigger signal (1-bit). Rising edge triggers the gate and delay.
Default: Must be connected
GATE Input 1 (integer) bit INT
Gate width in clock cycles (integer). Output stays HIGH for this many cycles.
Default: Must be connected
DELAY Input 1 (integer) bit INT
Delay in clock cycles (integer). Output is delayed by this amount relative to input.
Default: Must be connected
CLK Input 1 bit BIT
Clock signal for synchronous operation.
Default: Must be connected
RESET Input 1 bit BIT
Active-high reset. Clears internal state.
Default: Must be connected
OUT Output 1 bit BIT
Output signal (1-bit). Goes HIGH after DELAY cycles, stays HIGH for GATE cycles.

Properties

Property window

Max Delay Value MaxDelayValue

Set the amount of memory to reserve for this delay line

Maximum delay capacity. Allowed values: 64-65536. Reserves block RAM for delay line storage.

Default: 1024

Options: 64 128 256 512 1024 2048 4096 8192 16384 32756 65536

Functional description

The component combines a programmable delay line with a pulse width controller. When a rising edge is detected on IN, the block:

  1. Delays the pulse by DELAY clock cycles
  2. Asserts OUT=1 for GATE clock cycles
  3. Returns OUT=0

Typical application

Converts narrow input pulses into wider, delayed output pulses for trigger logic.

Timing

Latency = DELAY + 1 cycles (inherent delay line latency). Output width = GATE cycles.

Typical use cases

  • Trigger signal conditioning
  • Pulse width adjustment for logic gates
  • Delayed gate generation for coincidence windows