Gate and Delay (SW)

Introduction link

This block implements combined gate and delay functionality, delaying an input pulse by a programmable number of clock cycles and holding the output HIGH for a programmable gate width.

On a rising edge of IN:

• Output goes HIGH DELAY + 4 clock cycles later
• Output stays HIGH for GATE + 1 clock cycles
• Then returns LOW

The two added constants are fixed pipeline stages of the implementation, not rounding: see the Timing section for where they come from, a worked example, and the minimum interval between two triggers.

Pin Description link

Properties link

Functional description link

The component combines a programmable delay line with a pulse width controller. When a rising edge is detected on IN, the block:

1. Delays the event by DELAY clock cycles plus 4 fixed pipeline cycles
2. Asserts OUT=1 for GATE + 1 clock cycles
3. Returns OUT=0

The output pulse width is set by GATE alone: a one-cycle input pulse and a fifty-cycle input pulse both produce the same GATE + 1 cycles on OUT.

Typical application link

Converts narrow input pulses into wider, delayed output pulses for trigger logic.

Timing link

The figures below are the behaviour of the shipped RTL, measured in simulation (xsim 2020.2) over several input edges per run and the configurations (GATE, DELAY) = (5, 10), (1, 20), (12, 0), (8, 33), (6, 5) and (3, 6).

Latency = DELAY + 4 clock cycles link

Counting from the clock edge on which IN is first sampled HIGH, OUT goes HIGH on edge number DELAY + 4. The four fixed cycles are:

1. the rising-edge detector: IN is registered, and the edge is only visible one clock later, when the previous value is available for comparison;
2. the write of the detected event into the delay memory;
3. the first register stage of the block-RAM read port;
4. the second register stage of the block-RAM read port (READ_LATENCY = 2).

The DELAY pin adds its own cycles on top by moving the read pointer DELAY addresses behind the write pointer. The minimum total latency is therefore 4 clock cycles, reached with DELAY = 0.

Output width = GATE + 1 clock cycles link

The gate counter is loaded with GATE on the same edge that asserts the output bit, and the bit is cleared only on the edge after the counter has reached zero, so the pulse lasts one cycle more than the programmed value. To obtain a pulse of W cycles, program GATE = W - 1 (GATE = 0 is not a zero-width pulse - see below).

Worked example link

CLK = 100 MHz (10 ns period), DELAY = 96, GATE = 19. An input edge at t = 0 gives OUT HIGH from t = (96 + 4) x 10 ns = 1.00 us until t = 1.20 us, i.e. a 200 ns gate (20 cycles) one microsecond after the trigger. Conversely, to place a 200 ns gate exactly 1 us after the trigger at 100 MHz: DELAY = 100 - 4 = 96, GATE = 20 - 1 = 19.

Minimum re-trigger interval = GATE + 1 clock cycles link

While the gate is open the block is deaf: a rising edge on IN closer than GATE + 1 clock cycles to the previously accepted edge is ignored, not queued. Two edges exactly GATE + 1 cycles apart are both accepted and their output pulses abut, so they read as a single pulse of 2 x (GATE + 1) cycles.

GATE = 0 is a bypass, not a zero-width pulse link

With GATE = 0 the output is a direct combinational copy of IN: no delay, no gating, and the DELAY pin has no effect. Use GATE >= 1 for normal operation.

Changing GATE or DELAY at run time link

A new value on GATE or DELAY is latched one clock later and triggers an internal re-synchronisation that clears the delay-line write pointer. Samples travelling through the line across that clock are corrupted. Reprogram GATE and DELAY only while IN is idle; they are configuration inputs, not modulation inputs. DELAY must stay below MaxDelayValue.

Typical use cases link

• Trigger signal conditioning
• Pulse width adjustment for logic gates
• Delayed gate generation for coincidence windows