Constant Time

Introduction link

This block generates a constant time value represented as a number of clock cycles. The user specifies a time duration in human-readable units (ns, µs, ms, s), and the component automatically converts it to clock cycles based on the configured system clock frequency.

This simplifies timer and delay logic by abstracting clock cycle calculations:

$$ \mathrm{Clock\ Cycles} = \text{Time} \times \text{Clock\ Frequency} $$

The output is a bit-vector constant representing the integer number of clock cycles, suitable for direct use in counters, timers, and timeout logic.

Pin Description link

Properties link

Functional description link

The component implements a time-to-clock-cycle converter for constant time values. Given a time $T$, time unit, and clock frequency $f_{\text{clk}}$, the output is:

$$ \mathrm{CONST} = \lfloor T \times f_{\text{clk}} \rceil $$

where:

• $T$ = time value in selected units (ns, µs, ms, s)
• $f_{\text{clk}}$ = clock frequency in Hz
• $\lfloor \cdot \rceil$ = rounding to nearest integer

Time unit conversion link

The component supports four time units:

Clock cycle calculation link

The conversion formula depends on the clock frequency (specified in MHz):

$$ \text{Cycles} = \text{round}\left(T_{\text{seconds}} \times f_{\text{MHz}} \times 10^6\right) $$

Example: 100 µs @ 125 MHz

1. Convert to seconds: $100 \times 10^{-6} = 0.0001$ s
2. Multiply by frequency: $0.0001 \times 125 \times 10^6 = 12500$ cycles
3. Result: 0x30D4 (16-bit representation)

Bit width selection link

The N Bits property determines the output width. Choose sufficient bits to represent the maximum clock cycle count:

Required bits for time $T$ (seconds) at frequency $f$ (MHz): $$ \text{Bits needed} = \lceil \log_2(T \times f \times 10^6) \rceil $$

Common configurations:

Practical examples link

Example 1: 1 ms timeout @ 125 MHz link

  Value: 1
Unit: ms
Clock Frequency: 125 MHz
N Bits: 32

Calculation:
Cycles = 1e-3 × 125e6 = 125,000 = 0x1E848
Output: 32-bit constant = 0x0001E848
  

Example 2: 100 ns delay @ 200 MHz link

  Value: 100
Unit: ns
Clock Frequency: 200 MHz
N Bits: 16

Calculation:
Cycles = 100e-9 × 200e6 = 20 = 0x14
Output: 16-bit constant = 0x0014
  

Example 3: 5 second timer @ 50 MHz link

  Value: 5
Unit: s
Clock Frequency: 50 MHz
N Bits: 32

Calculation:
Cycles = 5 × 50e6 = 250,000,000 = 0xEE6B280
Output: 32-bit constant = 0x0EE6B280
  

Overflow handling link

If the calculated cycle count exceeds the maximum value for N Bits, the result is clamped to the maximum representable value:

$$ \text{Output} = \min(\text{Calculated Cycles}, 2^{\text{N Bits}} - 1) $$

Choose a larger bit width to avoid clamping.

Implementation details link

The VHDL implementation generates a hexadecimal constant:

  signal CONST : STD_LOGIC_VECTOR(N_Bits-1 downto 0);
CONST <= x"<hex_value>";
  

The conversion from time to clock cycles happens at compile time, so there is no runtime overhead.

Timing link

The component is purely combinational with zero latency:

The output is available immediately after FPGA configuration.

Typical use cases link

• Timeout timers: Define maximum wait times for communication protocols or watchdogs
• Delay generators: Create precise delays for sequencing or synchronization
• Pulse width modulators: Set duty cycle or period values in clock cycles
• Baud rate generators: Calculate divisor values for UART or serial interfaces
• Sampling intervals: Define fixed sampling periods for ADC or DAC systems
• Debounce timers: Set debounce durations for mechanical switches (typically 10-50 ms)
• Control loop periods: Define fixed update rates for PID or state machine loops

Design recommendations link

Choosing clock frequency link

Set Clock Frequency to match your FPGA’s system clock. For multi-clock designs, use the frequency of the domain where the constant will be used.

Choosing bit width link

• 16 bits: Sufficient for short delays (<1 ms @ 100 MHz)
• 24 bits: Good for medium delays (up to ~167 ms @ 100 MHz)
• 32 bits: Recommended for general-purpose timers (seconds range)
• 48/64 bits: Only needed for extremely long timeouts (minutes to hours)

Precision considerations link

The conversion rounds to the nearest integer cycle, so the actual time may differ slightly from the specified value:

$$ \text{Actual Time} = \frac{\text{Rounded Cycles}}{f_{\text{clk}}} $$

For high-precision timing, verify that the rounding error is acceptable.