Xilinx
TM
Block Preview

Introduction

The block computes

$$ \mathrm{OUT} = \min\bigl(\max(\mathrm{IN}, \mathrm{LO}), \mathrm{HI}\bigr) $$

and outputs the selected value. This is the difference with the boolean comparator blocks (Equal, Greater, Smaller, …), which only report the outcome of the test on a 1-bit flag: here the winning operand itself comes out.

The integer counterpart of this block is Limit, already in this plugin.

All ports are IEEE-754 numbers, single (32 bit) or double (64 bit) precision, selected by the FloatType property.

This is the time-multiplexed variant: the IN port carries TM samples packed side by side in one wide vector and one comparator is generated per slot, so all the slots are processed in the same clock cycle. Operand LO can either be time multiplexed as well or a single scalar compared against every slot, selected by the B_IsTM property.

Pin Description

IN Input Variable bit TM
IEEE-754 operand (32 or 64 bit, see FloatType). Width: one sample x TM Factor, slot 0 in the least significant bits.
Default: Must be connected
LO Input Variable bit TM
IEEE-754 operand (32 or 64 bit, see FloatType). When B_IsTM = YES this port is time multiplexed like IN; when NO it is a single scalar compared against every slot.
Default: Must be connected
HI Input Variable bit TM
IEEE-754 operand (32 or 64 bit, see FloatType). When C_IsTM = YES this port is time multiplexed; when NO it is a single scalar bound applied to every slot.
Default: Must be connected
IN_DV Input 1 bit BIT
Input data valid, active high. It is only carried through the pipeline to produce OUT_DV; tie it to ‘1’ for free running operation.
OUT Output 32 bit TM
The selected value. Packed like the inputs, one result per slot.
OUT_DV Output 1 bit BIT
Output data valid: IN_DV delayed by PipelineLength clock cycles.
CLK
Clock for the output pipeline registers. Not used when PipelineLength is 0.
RESET
Synchronous reset, active high: clears the pipeline registers.

Properties

Property window

Float Type FloatType

IEEE-754 precision of every port: Single (32 bit) or Double (64 bit).

IEEE-754 precision used by every port:

  • Single – 32 bit (1 sign, 8 exponent, 23 mantissa)
  • Double – 64 bit (1 sign, 11 exponent, 52 mantissa)

Default: Single

Options: Single Double

TM Factor TimeMultiplexing

Time multiplexing factor

Time multiplexing factor: 4, 8, 16 or 32 samples packed per port. One comparator is generated per slot.

Default: 4

Options: 4 8 16 32

LO is TM B_IsTM

YES: operand LO is time multiplexed like IN. NO: it is a single scalar value compared against every TM slot.

  • YES – operand LO is time multiplexed and is used slot by slot
  • NO – operand LO is a single scalar applied to every slot

Default: YES

Options: NO YES

HI is TM C_IsTM

YES: operand HI is time multiplexed. NO: it is a single scalar bound applied to every TM slot.

  • YES – operand HI is time multiplexed
  • NO – operand HI is a single scalar bound for every slot

Default: YES

Options: NO YES

Pipeline Length PipelineLength

Number of output register stages, i.e. the latency in clock cycles. 0 makes the block purely combinational.

Number of output register stages, i.e. latency in clock cycles (0 to 8). 0 makes the block purely combinational. Does not affect the result.

Default: 1

Options: 0 1 2 3 4 5 6 7 8

Functional description

$$ \mathrm{OUT} = \min\bigl(\max(\mathrm{IN}, \mathrm{LO}), \mathrm{HI}\bigr) $$

where

  • IN – IEEE-754 input operand
  • LO – IEEE-754 input operand
  • HI – IEEE-754 input operand
  • OUT – the selected operand, same format as the inputs

If LO is greater than HI the upper bound wins, because the lower bound is applied first and the upper bound second.

How the comparison is done

IEEE-754 was designed so that, within one sign, the ordering of the numbers is the same as the ordering of their raw bit patterns read as integers. Mapping the pattern through

$$ \mathrm{key}(x) = \begin{cases} \lnot x & \text{sign bit set}\ x \lor 2^{W-1} & \text{otherwise} \end{cases} $$

extends that property across the sign, so ONE unsigned integer comparison orders any two floats exactly. The block therefore costs a comparator and a multiplexer: no floating point IP, no DSP slice and no multi-cycle FPU latency.

Special values

  • NaN – follows the IEEE-754 minNum / maxNum convention: a NaN operand is ignored and the other one is returned. For Clamp, a NaN bound is ignored, while a NaN on IN passes through unchanged.
  • Infinities – ordered normally, so $-\infty$ is the smallest value and $+\infty$ the largest.
  • Signed zeros – ordered $-0 < +0$, so Min returns $-0$ and Max returns $+0$. The two are numerically equal; this is only a deterministic tie break.

Time multiplexing

The wide ports pack TM samples starting from the least significant bits:

    bits [W-1 : 0]            -> slot 0
  bits [2W-1 : W]           -> slot 1
  ...
  bits [TM*W-1 : (TM-1)*W]  -> slot TM-1

where W is the width of one sample. The slots are INDEPENDENT: one comparator is generated per slot and they never interact.

Implementation

Plain VHDL (Resources/Code/float_minmax.vhd), shared with the other operations of the same kind through the OP generic – the same way comparator.vhd already backs Equal, Greater and Smaller. No HLS is involved, so this block builds without Vitis HLS installed, and it uses no DSP slice.

Latency

PipelineLength sets the number of output register stages, i.e. the latency in clock cycles. Set it to 0 for a purely combinational block; raise it to help timing closure at high clock rates. It never changes the result.

Typical use cases

  • Protecting a downstream stage from out-of-range values
  • Programmable limiter with run-time thresholds
  • Enforcing a physical range on a computed quantity