Xilinx
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Introduction

The Word Serializer block converts one wide word into a sequence of narrower chunks. It is the counterpart of the Word Deserializer.

When a wide word is published on IN (with a one-cycle DV_IN pulse), the block splits it into InputSize / OutputSize chunks and emits them on OUT, one chunk per clock cycle, each accompanied by a DV_OUT pulse.

One input handshake:

  • IN + DV_IN + BUSY_IN - the wide source word.

One output handshake:

  • OUT + DV_OUT + BUSY_OUT - toward the downstream module.

Pin Description

IN Input 2-4096 bit BIT VECTOR
Wide input word. Width: Input word size bits. Captured when DV_IN = ‘1’ and the block is idle.
Default: Must be connected
DV_IN Input 1 bit BIT
Data Valid for the wide input word. Assert HIGH for one clock cycle to publish a word on IN. Must be held low while BUSY_IN is HIGH to avoid data loss.
Default: Must be connected
BUSY_OUT Input 1 bit BIT
Back-pressure from the downstream module. When HIGH, no chunk leaves and the block freezes with its partially shifted word preserved. Tie LOW if the downstream is never busy.
CLK Input 1 bit BIT
System clock input. All operations are synchronous to this clock. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous, active-high reset. Clears the shift register, the chunk counter and the output. Default: Global reset.
Default: Default Board Reset
BUSY_IN Output 1 bit BIT

Back-pressure toward the source.

  • HIGH (1): a word is still being serialized OR the downstream is asserting BUSY_OUT. The source should not publish a new word.
  • LOW (0): idle and ready to accept a new wide word.
OUT Output 1-4096 bit BIT VECTOR
Narrow output chunk. Width: Output word size bits. Valid when DV_OUT is HIGH.
DV_OUT Output 1 bit BIT
Data Valid output. Asserted HIGH for one clock cycle for each emitted chunk.

Properties

Property window

Input word size (bits) InputSize

Width of the wide IN word. Must be an integer multiple of, and larger than, the output word size

Width in bits of the wide IN word. Range: 2 to 4096, default 64. Must be a strict integer multiple of the output word size (checked on confirm). Changing this value re-designs the symbol.

Default: 64

Range: 2 – 4096

Output word size (bits) OutputSize

Width of each narrow OUT chunk. Must be an integer submultiple of, and smaller than, the input word size

Width in bits of each narrow OUT chunk. Range: 1 to 4096, default 32. Must be a strict integer submultiple of the input word size (checked on confirm). Changing this value re-designs the symbol.

Default: 32

Range: 1 – 4096

Chunk order BitOrder

Emit the most-significant chunk first (MSB word first) or the least-significant chunk first (LSB word first)

Order in which the chunks leave the block:

  • MSB word first (default): the most-significant chunk of the input word is emitted first.
  • LSB word first: the least-significant chunk is emitted first.

Default: MSB word first

Options: MSB word first LSB word first

Usage

Example

With Input word size = 64, Output word size = 32 the block produces two chunks per word:

    IN = 0xABBA123498765432  (one DV_IN pulse)

  Chunk order = MSB word first -> OUT = 0xABBA1234 , then 0x98765432
  Chunk order = LSB word first -> OUT = 0x98765432 , then 0xABBA1234

With Input = 64, Output = 16 it produces four chunks (0xABBA, 0x1234, 0x9876, 0x5432 in MSB-first order).

Constraint

Input word size must be a strict integer multiple of the Output word size (and therefore larger). This is enforced when the property window is confirmed: an invalid pair (e.g. 64 / 48) is rejected with an explanatory message and the window stays open.

Handshake rules

Both handshakes follow the standard SCI-Compiler DV / BUSY protocol:

  1. The source raises DV_IN = ‘1’ for one clock cycle to publish a wide word. It is accepted only while the block is idle and the downstream is free.
  2. BUSY_IN is asserted while a word is being serialized (chunks still pending) or while the downstream asserts BUSY_OUT. In both cases the source must not publish a new word.
  3. Each cycle with BUSY_OUT = ‘0’ and chunks still pending emits one chunk on OUT and pulses DV_OUT.
  4. BUSY_OUT = ‘1’ freezes the block: the internal shift register and the chunk counter keep their value and no chunk leaves.

Timing

All outputs are registered and update on the rising edge of clk. The first chunk appears one clock after the word is latched; the remaining chunks follow on consecutive clocks (longer if BUSY_OUT stalls the stream). Throughput is up to one chunk per clock.

Reset

Reset is active-high and synchronous. RESET = ‘1’ clears the shift register, the chunk counter and the output, so a downstream flush never leaves a half-serialized word suspended inside the block.

Resources & Timing

  • Latency: 1 clock from load to first chunk, then 1 clock per chunk

  • Throughput: Up to 1 chunk per clock cycle when the downstream is not busy

Fully synchronous, no external primitives, no FIFO. Uses one InputSize shift register and a small chunk counter. Resource usage scales with InputSize.