Introduction

SCI-Compiler is not just a graphical programming tool — it’s a complete automated design flow that transforms your block diagram into working hardware and ready-to-use software libraries.

Unlike traditional FPGA development where you manually navigate through multiple complex tools, SCI-Compiler orchestrates the entire process automatically. You press “Compile” and SCI-Compiler handles everything from code generation to hardware programming.

From idea to working hardware in minutes, not months.

The Traditional FPGA Development Challenge

Developing custom FPGA firmware traditionally requires expertise in multiple domains and tools:

Challenge Traditional Approach Time Investment
HDL coding Write thousands of lines of VHDL/Verilog Weeks to months
Testbench development Create simulation environments Days to weeks
Synthesis & Implementation Configure tool settings, fix timing errors Hours to days
Driver development Write low-level hardware access code Weeks
Software integration Develop APIs and data structures Weeks

For a scientist or engineer focused on signal processing algorithms, this represents a prohibitive barrier to entry.

SCI-Compiler eliminates these barriers entirely.

The SCI-Compiler Workflow

SCI-Compiler implements a fully automated 6-stage design flow that runs with a single button press:

Complete Design Flow Overview 

  ┌─────────────────────────────────────────────────────────────────┐
│  STAGE 1: Graphical Design Entry                               │
│  User connects functional blocks in visual editor               │
└────────────────────┬────────────────────────────────────────────┘
                     │
                     ▼
┌─────────────────────────────────────────────────────────────────┐
│  STAGE 2: VHDL Code Generation                                 │
│  SCI-Compiler automatically generates HDL from block diagram    │
└────────────────────┬────────────────────────────────────────────┘
                     │
                     ▼
┌─────────────────────────────────────────────────────────────────┐
│  STAGE 3: FPGA Compilation (Synthesis, Implementation)         │
│  Xilinx Vivado or Intel Quartus execute in background          │
└────────────────────┬────────────────────────────────────────────┘
                     │
                     ▼
┌─────────────────────────────────────────────────────────────────┐
│  STAGE 4: Bitstream Conversion                                 │
│  Convert to platform-specific configuration file               │
└────────────────────┬────────────────────────────────────────────┘
                     │
                     ▼
┌─────────────────────────────────────────────────────────────────┐
│  STAGE 5: Firmware Download                                    │
│  Program target hardware via USB/Ethernet/VME                  │
└────────────────────┬────────────────────────────────────────────┘
                     │
                     ▼
┌─────────────────────────────────────────────────────────────────┐
│  STAGE 6: Software Library Generation                          │
│  Generate JSON firmware description for SciSDK integration     │
└─────────────────────────────────────────────────────────────────┘

Design Flow Stages Explained

Stage 1: Graphical Design Entry

Programming with SCI-Compiler is analogous to assembling an experimental setup rather than writing software. You place functional macro-blocks and connect them together, just like connecting physical NIM/CAMAC modules with cables.

User Actions:

  • Drag and drop processing blocks from the library
  • Connect blocks with wires (signals)
  • Configure block parameters (thresholds, gains, timing, etc.)
  • Add readout endpoints (Oscilloscope, Spectrum, List, etc.)
  • Define registers for runtime configuration

SCI-Compiler Block Library Categories:

Category Example Blocks
I/O Interface ADC inputs, Digital I/O, board-specific interfaces
Signal Processing Triggers, shapers, filters, peak detectors, baseline
Energy Measurement Trapezoidal filter, charge integration (QDC), CR-RC²
Time Measurement TDC, ToF, ToT, timestamp generators
Data Acquisition Oscilloscope, Spectrum, List, Digitizer, Custom Packet
Logic Gates, counters, timers, flip-flops, state machines
Math Arithmetic, comparators, multipliers, dividers, FFT

Design Paradigm:

Unlike software development, where you think in terms of sequential instructions, FPGA design with SCI-Compiler is spatial — you visualize how data flows through parallel processing pipelines.

Stage 2: VHDL Code Generation

When you press “Compile,” SCI-Compiler analyzes your block diagram and automatically generates synthesizable VHDL code.

What SCI-Compiler Generates:

2.1 Component Instantiation

Each block in your diagram becomes a VHDL component with ports and generics:

vhdl 
  -- Example: Trapezoidal Filter instantiation
U_TRAPFILTER: entity work.TrapezoidalFilter
  generic map (
    INPUT_WIDTH     => 14,
    RISE_TIME       => 2000,
    FLAT_TOP        => 1000,
    TM_FACTOR       => 1
  )
  port map (
    clk             => clk_acq,
    reset           => reset,
    data_in         => adc_ch0_data,
    data_in_valid   => adc_ch0_valid,
    data_out        => trap_output,
    data_out_valid  => trap_valid
  );

2.2 Interconnect Wiring

SCI-Compiler generates all signal connections between blocks:

vhdl 
  -- Signal declarations for block interconnections
signal adc_ch0_data       : std_logic_vector(13 downto 0);
signal trap_output        : std_logic_vector(31 downto 0);
signal trigger_output     : std_logic;
signal spectrum_address   : std_logic_vector(15 downto 0);

2.3 Clock Domain Management

Automatic handling of multiple clock domains with proper synchronization:

vhdl 
  -- Clock domain crossing for control registers
U_CDC_THRESHOLD: entity work.cdc_synchronizer
  generic map (WIDTH => 16)
  port map (
    clk_src   => clk_bus,      -- Register write clock
    clk_dst   => clk_acq,      -- Processing clock
    data_in   => reg_threshold,
    data_out  => threshold_synced
  );

2.4 Register Map

Generate memory-mapped registers for configuration and readout:

vhdl 
  -- Register address decoder
process(clk_bus, reset)
begin
  if reset = '1' then
    reg_threshold <= x"03E8";  -- Default: 1000
    reg_gate_width <= x"0064"; -- Default: 100
  elsif rising_edge(clk_bus) then
    if bus_write = '1' then
      case bus_address is
        when x"0000" => reg_threshold <= bus_wdata(15 downto 0);
        when x"0004" => reg_gate_width <= bus_wdata(15 downto 0);
        when others => null;
      end case;
    end if;
  end if;
end process;

2.5 Endpoint Integration

Integrate readout endpoints (Oscilloscope, Spectrum, etc.) with the framework:

vhdl 
  -- Spectrum endpoint integration
U_SPECTRUM: entity work.SpectrumEndpoint
  generic map (
    BINS          => 1024,
    BIN_WIDTH     => 32,
    ENDPOINT_ID   => 16#0001#
  )
  port map (
    clk           => clk_acq,
    reset         => reset,
    data_in       => energy_value,
    data_valid    => energy_valid,
    -- Memory-mapped interface
    mm_clk        => clk_bus,
    mm_address    => mm_addr,
    mm_read       => mm_rd,
    mm_readdata   => mm_rdata,
    mm_write      => mm_wr,
    mm_writedata  => mm_wdata
  );

Code Generation Statistics:

A typical SCI-Compiler design generates:

  • 3,000 - 15,000 lines of VHDL code
  • 20 - 200 component instantiations
  • 100 - 1,000 signal declarations
  • Complete register map with auto-generated addresses

Time to generate: Typically < 5 seconds

Stage 3: FPGA Compilation

SCI-Compiler executes the FPGA vendor’s compilation tool (Xilinx Vivado or Intel Quartus) in the background to transform VHDL into a physical circuit implementation.

Why You Need Xilinx Vivado / Intel Quartus

Question: Why do I need to install Vivado or Quartus if SCI-Compiler generates the code?

Answer: FPGA manufacturers invest millions of dollars developing compilation tools that transform HDL into optimized FPGA configuration files. This process requires:

  • Deep knowledge of the FPGA internal structure (proprietary, undocumented)
  • Advanced algorithms for synthesis, placement, and routing
  • Timing analysis engines to meet clock constraints
  • Technology mapping specific to each FPGA family

SCI-Compiler is a code generator, not an FPGA compiler.

However, SCI-Compiler fully integrates with Vivado/Quartus:

  • Creates complete project files automatically
  • Executes tools in batch mode
  • Monitors compilation progress
  • Captures error/warning messages
  • Extracts resource utilization reports

From the user’s perspective, SCI-Compiler appears as a fully integrated IDE.

Compilation Sub-Stages

The FPGA compilation process consists of several automated stages:

  ┌──────────────────────────────────────────────────────────────┐
│  3.1 SYNTHESIS                                               │
│  Convert VHDL to technology-independent netlist             │
│  • Elaborate design hierarchy                               │
│  • Optimize logic (e.g., constant propagation, CSE)         │
│  • Infer registers, RAMs, DSPs                              │
└────────────────────┬─────────────────────────────────────────┘
                     │
                     ▼
┌──────────────────────────────────────────────────────────────┐
│  3.2 TECHNOLOGY MAPPING                                      │
│  Map netlist to FPGA primitives (LUTs, FFs, BRAMs, DSPs)    │
│  • Map logic functions to LUT configurations                │
│  • Pack registers into CLB slices                           │
│  • Allocate BRAM and DSP blocks                             │
└────────────────────┬─────────────────────────────────────────┘
                     │
                     ▼
┌──────────────────────────────────────────────────────────────┐
│  3.3 PLACEMENT                                               │
│  Assign logic to physical locations on FPGA                 │
│  • Optimize for timing, minimize routing congestion         │
│  • Consider clock regions and I/O banks                     │
└────────────────────┬─────────────────────────────────────────┘
                     │
                     ▼
┌──────────────────────────────────────────────────────────────┐
│  3.4 ROUTING                                                 │
│  Connect placed components using programmable interconnect  │
│  • Route critical paths first                               │
│  • Balance routing delay                                    │
└────────────────────┬─────────────────────────────────────────┘
                     │
                     ▼
┌──────────────────────────────────────────────────────────────┐
│  3.5 TIMING ANALYSIS                                         │
│  Verify design meets timing constraints                     │
│  • Check setup/hold times                                   │
│  • Report worst negative slack (WNS)                        │
│  • Identify failing paths                                   │
└────────────────────┬─────────────────────────────────────────┘
                     │
                     ▼
┌──────────────────────────────────────────────────────────────┐
│  3.6 BITSTREAM GENERATION                                    │
│  Create binary configuration file                           │
│  • Encode LUT contents, routing switches, I/O settings      │
│  • Add CRC and encryption (if enabled)                      │
└──────────────────────────────────────────────────────────────┘

Compilation Time:

  • Simple designs: 5-15 minutes
  • Complex designs: 30-90 minutes
  • Very large designs: 2-4 hours

Solution: Use SCI-Compiler’s Remote Compilation Service to offload compilation to CAEN’s dedicated servers.

Resource Utilization Report

After compilation, SCI-Compiler displays FPGA resource usage:

  Resource Utilization Report
───────────────────────────────────────────────────────────
Resource              Used      Available    Utilization
───────────────────────────────────────────────────────────
Slice LUTs            42,853    101,440      42.2%
Slice Registers       38,421    202,880      18.9%
Block RAM (36Kb)      78        140          55.7%
DSP48 Slices          64        240          26.7%
───────────────────────────────────────────────────────────
Timing Summary
───────────────────────────────────────────────────────────
Worst Negative Slack: 0.234 ns  ✓ TIMING MET
Clock: clk_acq (125 MHz, 8.000 ns period)

Stage 4: Bitstream Conversion

The output from Vivado/Quartus is a generic bitstream (.bit, .sof file) that must be converted to a platform-specific configuration file compatible with the target hardware.

Why Conversion is Needed:

Each hardware platform has its own bootloader and storage format:

Platform Bootloader Configuration File Storage
DT5560 USB Bootloader .rbf (Raw Binary) Flash memory
R5560 Zynq FSBL boot.bin (Zynq boot image) SD card / QSPI
V2495 EPCS Flash .rpd (Raw Programming Data) EPCS serial flash
DT1260 USB DFU .bin (DFU format) Internal flash

SCI-Compiler automatically:

  • Detects the target platform
  • Invokes the appropriate conversion tools
  • Packages firmware with framework components
  • Generates platform-specific header files

Example: Zynq Boot Image Creation

For Zynq-based boards (DT5560, R5560, V2730, etc.), SCI-Compiler creates a complete boot image containing:

  boot.bin (Zynq Boot Image)
├── FSBL (First Stage Boot Loader)
├── Bitstream (FPGA configuration)
└── U-Boot / Bare-metal application

Tools used internally:

  • bootgen (Xilinx)
  • vivado -mode batch for .bit → .bin conversion
  • Custom Nuclear Instruments packaging utilities

Stage 5: Firmware Download

Once the configuration file is ready, SCI-Compiler programs the target hardware automatically over the selected interface (USB, Ethernet, VME).

Download Methods:

USB Programming 

  PC ──USB cable──► Digitizer (DT5560, DT1260, etc.)

Protocol: USB 2.0/3.0
Speed: 10-30 MB/s
Time: 5-30 seconds (depending on bitstream size)

Ethernet Programming 

  PC ──Ethernet──► Digitizer (R5560, V2730, etc.)

Protocol: TCP/IP
Speed: 50-100 MB/s (1 Gbps link)
Time: 3-15 seconds

VME Programming 

  PC ──VME Controller──► VME Crate ──► Module (V2495, V2730, etc.)

Protocol: VME bus
Speed: 2-10 MB/s
Time: 20-60 seconds

Programming Sequence:

  1. Establish connection to target hardware
  2. Enter bootloader mode (if not already)
  3. Erase flash memory (if persistent storage)
  4. Transfer bitstream in chunks with CRC verification
  5. Verify programming by reading back configuration
  6. Trigger FPGA reconfiguration from new bitstream
  7. Verify firmware version and endpoint enumeration

What Happens During FPGA Configuration:

When the FPGA receives the bitstream:

  • Configuration memory cells are programmed (~25 million bits for Kintex-7)
  • LUT truth tables are loaded
  • Routing switches are set to connect logic
  • I/O buffers are configured with voltage standards
  • Clock PLLs lock to reference frequencies
  • Block RAMs are initialized (if specified)

Time: Typically 100-500 ms for FPGA configuration after bitstream transfer.

Stage 6: Software Library Generation

The final stage generates a JSON firmware description file (RegisterFile.json) that enables seamless integration with SciSDK.

What is Generated

RegisterFile.json contains:

  • Endpoint enumeration: All Oscilloscope, Spectrum, List, Register blocks
  • Memory map: Base addresses, register offsets, bit fields
  • Data structures: Format of acquired data, metadata fields
  • Capabilities: Parameters, ranges, modes for each endpoint

Example RegisterFile.json Structure:

json 
  {
  "Device": "DT5560",
  "Magic": "593AE14D",
  "Project": "my_mca_project",
  "Registers": [
    {
      "Name": "threshold",
      "Type": null,
      "Address": 0,
      "Version": null,
      "RegionSize": 1,
      "Description": "Trigger threshold in ADC counts",
      "Category": "Undefined"
    },
    {
      "Name": "gate_width",
      "Type": null,
      "Address": 1,
      "Version": null,
      "RegionSize": 1,
      "Description": "Integration gate width",
      "Category": "Undefined"
    },
    {
      "Name": "baseline_samples",
      "Type": null,
      "Address": 2,
      "Version": null,
      "RegionSize": 1,
      "Description": "Number of samples for baseline calculation",
      "Category": "Undefined"
    }
  ],
  "MMCComponents": [
    {
      "Name": "Spectrum_0",
      "Type": "Spectrum",
      "Address": 196608,
      "Version": "1.0.1.0",
      "bins": 16384,
      "CountsBit": 32,
      "Registers": [
        {
          "Name": "STATUS",
          "Type": null,
          "Address": 262144,
          "Version": null,
          "RegionSize": 1,
          "Description": "Spectrum status register",
          "Category": "Undefined"
        },
        {
          "Name": "CONFIG",
          "Type": null,
          "Address": 262145,
          "Version": null,
          "RegionSize": 1,
          "Description": "Spectrum configuration",
          "Category": "Undefined"
        },
        {
          "Name": "CONFIG_REBIN",
          "Type": null,
          "Address": 262147,
          "Version": null,
          "RegionSize": 1,
          "Description": "Rebin factor",
          "Category": "Undefined"
        }
      ]
    },
    {
      "Name": "Oscilloscope_0",
      "Type": "Oscilloscope",
      "Address": 1024,
      "Version": "1.0.0.0",
      "nsamples": 1024,
      "Channels": 1,
      "WordSize": 16,
      "WordEnob": 16,
      "AnalogInputs": 1,
      "DigitalInputs": 4,
      "SamplingFrequency": 125000000,
      "TimeMultiplexing": 1,
      "DecimatorMax": 256,
      "DecimatorAveraging": false,
      "Registers": [
        {
          "Name": "READ_STATUS",
          "Type": "Register",
          "Address": 2048,
          "Version": "",
          "RegionSize": 1,
          "Description": "Oscilloscope readout status",
          "Category": "Undefined"
        },
        {
          "Name": "CONFIG_TRIGGER_MODE",
          "Type": "Register",
          "Address": 2050,
          "Version": "",
          "RegionSize": 1,
          "Description": "Trigger mode configuration",
          "Category": "Undefined"
        },
        {
          "Name": "CONFIG_PRETRIGGER",
          "Type": "Register",
          "Address": 2051,
          "Version": "",
          "RegionSize": 1,
          "Description": "Pretrigger samples",
          "Category": "Undefined"
        }
      ]
    }
  ]
}

Integration with SciSDK

SciSDK reads this JSON file to:

  • Auto-discover all firmware components
  • Generate Python/C/C++ classes for each endpoint
  • Map memory addresses automatically
  • Decode binary data into structured formats
  • Provide high-level APIs (e.g., ReadSpectrum(), ConfigureTrigger())

User benefit: Change your SCI-Compiler design, recompile, and your existing Python/C++ code continues to work — no driver regeneration needed.

Example: Using Generated Firmware in Python

python 
  from scisdk.scisdk import SciSDK

# Connect to board using auto-generated JSON
sdk = SciSDK()
sdk.AddNewDevice("usb:10500", "dt5560", "board0", "RegisterFile.json")

# Configure threshold register (auto-discovered from JSON)
sdk.SetParameter("board0:/Registers/threshold", 1500)

# Read spectrum endpoint (data format from JSON)
res, buf = sdk.AllocateBuffer("board0:/MMCComponents/Spectrum_0")
sdk.ReadData("board0:/MMCComponents/Spectrum_0", buf)

# Access decoded data
spectrum = buf.data  # NumPy array with 1024 bins
print(f"Total counts: {sum(spectrum)}")

No manual driver coding. No register address lookups. Just works.

SCI-Compiler Outputs Summary

After completing the design flow, SCI-Compiler produces:

Output Description Use
VHDL Project Complete synthesizable VHDL code Review, simulation, version control
Vivado/Quartus Project Tool-specific project files Modify advanced settings if needed
Bitstream (.bit) Generic FPGA configuration Alternative programming methods
Configuration file Platform-specific firmware Program target hardware
RegisterFile.json Firmware description SciSDK integration
Resource Report FPGA utilization, timing Optimize design

Local vs Remote Compilation

SCI-Compiler offers two compilation modes:

Local Compilation

Advantages:

  • Full control over compilation process
  • No internet connection required
  • Proprietary designs remain on your PC

Requirements:

  • Xilinx Vivado or Intel Quartus installed
  • 20-50 GB disk space per tool installation
  • 8-16 GB RAM recommended
  • 30-90 minutes compilation time (typical)

Remote Compilation

Advantages:

  • No local FPGA tools installation needed
  • Faster compilation on CAEN’s dedicated servers
  • Save disk space and local computational resources
  • Compile from low-power laptops

How it works:

  1. SCI-Compiler packages your design and uploads to CAEN servers
  2. Dedicated server compiles using latest tool versions
  3. Email notification when compilation completes
  4. Download bitstream and program hardware directly

Security: Designs are encrypted during transmission and automatically deleted from servers after download.

Portal: https://community.sci-compiler.com/login

Design Flow Best Practices

1. Start with Simulation

Before compiling to hardware, use SCI-Compiler’s integrated simulator:

  • Verify logic with test signals
  • Debug algorithms with detector emulator
  • Iterate quickly (seconds vs hours)

2. Use Hierarchical Design

For complex systems:

  • Create sub-designs for reusable modules
  • Simplify top-level diagram
  • Enable team collaboration

3. Check Resource Utilization

Monitor FPGA resource usage:

  • < 70% LUT utilization: Safe, room for modifications
  • 70-85% utilization: Acceptable, timing may be challenging
  • > 85% utilization: Risky, routing congestion, timing failures

4. Version Control Your Designs

  • Use MySci-Compiler portal for cloud project storage
  • Export .scproj files to Git repositories
  • Track firmware versions with meaningful names

5. Test Incrementally

  • Start with simple designs (e.g., digital counter)
  • Add complexity gradually
  • Use Resource Explorer to verify each stage

Troubleshooting Common Issues

Compilation Fails

Timing not met:

  • Reduce clock frequency
  • Simplify complex combinational logic
  • Add pipeline registers in critical paths

Resource overflow:

  • Reduce buffer sizes (Oscilloscope, List)
  • Decrease spectrum bins
  • Remove unused endpoints

HDL errors:

  • Check block connections (all inputs connected)
  • Verify bit widths match
  • Review SCI-Compiler error messages

Programming Fails

Device not found:

  • Check USB/Ethernet cable
  • Verify drivers installed
  • Check firewall settings (for Ethernet)

CRC error during programming:

  • Try slower programming speed
  • Check cable quality
  • Restart board and retry

Firmware Doesn’t Work as Expected

No data from endpoints:

  • Verify triggers are enabled
  • Check threshold settings
  • Use Resource Explorer to monitor signals

Incorrect data values:

  • Review signal scaling and units
  • Check for saturation in filters
  • Verify input range matches ADC settings

Summary

SCI-Compiler’s automated design flow transforms FPGA development from a months-long expert task into an accessible, rapid prototyping process:

Traditional FPGA Flow SCI-Compiler Flow
Write 10,000+ lines of VHDL Draw block diagram
Debug synthesis errors Pre-validated IP blocks
Fix timing constraints Automated timing closure
Write device drivers Auto-generated SciSDK integration
Weeks to months Hours to days

The six-stage automated workflow — from graphical design entry through VHDL generation, FPGA compilation, bitstream conversion, firmware download, to software library generation — runs with a single button press.

Focus on your algorithm. Let SCI-Compiler handle the complexity.