Xilinx
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Introduction

The Word Deserializer block assembles one wide word out of a stream of narrower chunks. It is the counterpart of the Word Serializer.

Each chunk is published on IN with a one-cycle DV_IN pulse. The pulses may be back-to-back or separated by an arbitrary number of clock cycles. When the last chunk of a word arrives, the block presents the assembled word on OUT with a single DV_OUT pulse.

One input handshake:

  • IN + DV_IN + BUSY_IN - the narrow source chunks.

One output handshake:

  • OUT + DV_OUT + BUSY_OUT - toward the downstream module.

Pin Description

IN Input 1-4096 bit BIT VECTOR
Narrow input chunk. Width: Input word size bits. Captured when DV_IN = ‘1’.
Default: Must be connected
DV_IN Input 1 bit BIT
Data Valid for the narrow input chunk. Assert HIGH for one clock cycle to publish a chunk on IN. Pulses may be adjacent or arbitrarily far apart. Must be held low while BUSY_IN is HIGH to avoid data loss.
Default: Must be connected
BUSY_OUT Input 1 bit BIT
Back-pressure from the downstream module. When HIGH, a finished word is held inside the block and no new chunk is accepted. Tie LOW if the downstream is never busy.
CLK Input 1 bit BIT
System clock input. All operations are synchronous to this clock. Default: Acquisition clock.
Default: Default Board Clock
RESET Input 1 bit BIT
Synchronous, active-high reset. Clears the accumulator, the chunk counter and any pending output word. Default: Global reset.
Default: Default Board Reset
BUSY_IN Output 1 bit BIT

Back-pressure toward the source.

  • HIGH (1): a finished word is waiting to be forwarded OR the downstream is asserting BUSY_OUT. The source should not publish the next chunk.
  • LOW (0): ready to accept the next chunk.
OUT Output 2-4096 bit BIT VECTOR
Assembled wide output word. Width: Output word size bits. Valid when DV_OUT is HIGH.
DV_OUT Output 1 bit BIT
Data Valid output. Asserted HIGH for one clock cycle when a fully assembled word is published on OUT.

Properties

Property window

Input word size (bits) InputSize

Width of each narrow IN chunk. Must be an integer submultiple of, and smaller than, the output word size

Width in bits of each narrow IN chunk. Range: 1 to 4096, default 32. Must be a strict integer submultiple of the output word size (checked on confirm). Changing this value re-designs the symbol.

Default: 32

Range: 1 – 4096

Output word size (bits) OutputSize

Width of the assembled wide OUT word. Must be an integer multiple of, and larger than, the input word size

Width in bits of the assembled wide OUT word. Range: 2 to 4096, default 64. Must be a strict integer multiple of the input word size (checked on confirm). Changing this value re-designs the symbol.

Default: 64

Range: 2 – 4096

Chunk order BitOrder

First received chunk becomes the most-significant part (MSB word first) or the least-significant part (LSB word first) of the assembled word

Where the first received chunk lands in the assembled word:

  • MSB word first (default): the first chunk becomes the most-significant part of the output word.
  • LSB word first: the first chunk becomes the least-significant part of the output word.

Default: MSB word first

Options: MSB word first LSB word first

Usage

Example

With Input word size = 32, Output word size = 64 the block collects two chunks per word:

    IN = 0xABBACAFE (DV pulse) ... later ... IN = 0x12345678 (DV pulse)

  Chunk order = MSB word first -> OUT = 0xABBACAFE12345678
  Chunk order = LSB word first -> OUT = 0x12345678ABBACAFE

The gap between the two DV_IN pulses does not matter: the word is published as soon as (and only when) the final chunk is available.

Constraint

Output word size must be a strict integer multiple of the Input word size (and therefore larger). This is enforced when the property window is confirmed: an invalid pair (e.g. 48 / 32) is rejected with an explanatory message and the window stays open.

Handshake rules

Both handshakes follow the standard SCI-Compiler DV / BUSY protocol:

  1. The source raises DV_IN = ‘1’ for one clock cycle to publish a chunk. Chunks are shifted into an accumulator in arrival order.
  2. The chunk that completes a word latches the full word and raises DV_OUT one clock later (when BUSY_OUT allows).
  3. BUSY_IN is asserted while a finished word is still waiting to be forwarded or while the downstream asserts BUSY_OUT. In both cases the source must not publish the next chunk.
  4. BUSY_OUT = ‘1’ holds the finished word inside the block until the downstream is ready.

Timing

All outputs are registered and update on the rising edge of clk. A word becomes available one clock after its last chunk is accepted (longer if BUSY_OUT is holding it back).

Reset

Reset is active-high and synchronous. RESET = ‘1’ clears the accumulator, the chunk counter and any pending output word, so a downstream flush never leaves a half-assembled word suspended inside the block.

Resources & Timing

  • Latency: 1 clock from the last chunk to the assembled word

  • Throughput: One assembled word every InputSize/OutputSize chunks

Fully synchronous, no external primitives, no FIFO. Uses one OutputSize accumulator, a one-word output register and a small chunk counter. Resource usage scales with OutputSize.