Block Preview

Introduction

This block generates a constant bit-vector value that remains fixed throughout operation. The constant is defined at design time and synthesized directly into the FPGA logic as a hardwired value.

The component accepts values in multiple formats:

  • Hexadecimal: 0xFF, 0x100, 0xDEADBEEF
  • Binary: 0b10101010, 0b11110000
  • Decimal: 255, 1024, 3735928559

The output is a purely combinational constant with zero clock latency, available immediately after FPGA configuration.

Pin Description

CONST Output Variable (BitSize property) bit BIT VECTOR

Constant bit-vector output, always combinational (zero latency). Width: Configurable via BitSize property (1 to 10,000,000,000 bits).

The output value is fixed at design time and remains constant during operation. No clock or enable signals required.

Properties

Property window

Number of bits BitSize

Set the number of bits for the output constant signal

Number of bits in the output constant bit-vector. Range: 1 to 10,000,000,000. Determines the width of the CONST output pin.

Default: 8

Value Value

Set the value of the constant. Use 0x for exadecimal Use 0b for binary code

Constant value in hexadecimal (0x…), binary (0b…), or decimal format. Examples: 0xFF, 0b10101010, 255. The value is automatically resized to match BitSize.

Default: 0

Functional description

The component implements a constant bit-vector source in VHDL. The value is defined at compile time and hardwired into the design:

$$ \mathrm{CONST} = V $$

where $V$ is the user-specified constant value, represented as a bit-vector of configurable width.

Value formats

The component supports three input formats:

  • Hexadecimal (0x prefix): Most compact for large values

      Value: 0xFF        → 8-bit: "11111111"
Value: 0x1234      → 16-bit: "0001001000110100"

  • Binary (0b prefix): Explicit bit-by-bit specification

      Value: 0b10101010  → 8-bit: "10101010"
Value: 0b1111      → 4-bit: "1111"

  • Decimal (no prefix): Standard integer notation

      Value: 255         → 8-bit: "11111111"
Value: 1024        → needs ≥11 bits

Bit width and truncation

The BitSize property determines the output width. If the specified value requires more bits than BitSize, the VHDL resize function automatically truncates the most significant bits:

  Value: 0x1FF (9 bits needed)
BitSize: 8
Result: 0xFF (MSB truncated)

If the value is smaller than BitSize, it is zero-extended to the left:

  Value: 0xF (4 bits)
BitSize: 8
Result: 0x0F (zero-extended)

Implementation details

The VHDL implementation uses different conversion methods based on the input format:

  • Hexadecimal: std_logic_vector(resize(unsigned'(x"..."), BitSize))
  • Binary: std_logic_vector(resize(unsigned'("..."), BitSize))
  • Decimal: conv_std_logic_vector(value, BitSize)

All formats guarantee correct bit-width matching through automatic resizing.

Timing

The component is purely combinational with zero latency:

Property Latency (clock cycles)
Constant Bit-Vector 0

The output is available immediately after FPGA configuration and does not depend on any clock signal.

Typical use cases

  • Bit masks: Define fixed patterns for masking operations (e.g., 0xFF00)
  • Lookup table initialization: Provide constant indices or addresses
  • Protocol constants: Define fixed headers, magic numbers, or identifiers
  • Test vectors: Generate known patterns for simulation and verification
  • Default values: Supply reset or initialization values to other components
  • Bit field manipulation: Create constants for setting/clearing specific bits

Example configurations

Example 1: 8-bit hexadecimal mask 

  BitSize: 8
Value: 0xAA
Output: "10101010" (alternating bits)

Example 2: 16-bit protocol header 

  BitSize: 16
Value: 0xFACE
Output: "1111101011001110" (fixed packet header)

Example 3: Binary bit pattern 

  BitSize: 4
Value: 0b1010
Output: "1010" (explicit bit pattern)

Example 4: Decimal constant 

  BitSize: 12
Value: 2048
Output: "100000000000" (2^11)