Accumulator Full (TM)
Time-multiplexed accumulator maintaining independent accumulator registers for each TM phase. Outputs TM data with configurable accumulator bit width (8-64 bits) and input width (4-32 bits). Implemented using Xilinx HLS with 3 clock cycles latency. Ideal for parallel channel integration.
Introduction
This block implements N independent accumulators (where N = TM Factor), one for each time-multiplexed channel. Each accumulator maintains its own running sum, producing a TM output stream.
On every rising edge of CLK, for each TM phase $i$:
$$ \mathrm{OUT}_i[n] = \mathrm{OUT}_i[n-1] + \mathrm{IN}_i[n], $$
A synchronous active-high RESET clears all accumulator registers to zero.
The accumulator bit width can be wider than the input to provide headroom
and prevent overflow.
Pin Description
Input bits × TM Factor
Each TM lane feeds its corresponding accumulator.
Accumulator bits × TM Factor
Each TM lane contains the independent running sum for that channel.
Valid after 3 clock cycles from input.
Properties
Set the number of bits of each input sample
Number of bits per input sample ($N_\text{in}$). Range: 4 – 32. Determines input dynamic range.Default: 16
Range: 4 – 32
Set the number of bits of the accumulator output
Width of each accumulator register ($N_\text{acc}$). Range: 8 – 64. Should typically be larger than Input bits to prevent overflow.
Overflow headroom: $2^{(N_\text{acc} - N_\text{in})}$ samples.
Default: 48
Range: 8 – 64
Select the sign/unsign of the input
Arithmetic type of input and accumulator:
- UNSIGNED → Non-negative integers, wrap at $2^{N}-1$
- SIGNED → Two’s complement, range $[-2^{N-1}, 2^{N-1}-1]$
Accumulator preserves sign type.
Default: UNSIGNED
Options: UNSIGNED SIGNED
Select the Time Multiplexing factor (samples per word)
Number of time-multiplexed phases (parallel accumulators). Allowed values: 2, 4, 8, 16, 32.
Each TM lane has an independent accumulator register, resulting in N parallel integration channels.
Default: 8
Options: 2 4 8 16 32
Functional description
The component implements parallel accumulators using Xilinx HLS, with each TM lane having its own independent accumulator register.
Operation
For each TM phase $i \in [0, N-1]$:
$$ \text{acc}_i[n] = \text{acc}_i[n-1] + x_i[n], \qquad \text{acc}_i[-1] = 0 $$
where:
- $x_i[n]$ →
IN(TM phase $i$) - $\text{acc}_i[n]$ →
OUT(TM phase $i$) - $N$ → TM Factor
Accumulator width
The accumulator register width (Accumulator bits) can be configured independently from the input width (Input bits):
- AccBits > InBits: Provides overflow headroom (recommended)
- AccBits = InBits: Modulo-$2^N$ arithmetic (wrap-around on overflow)
For unsigned inputs of width $w_\text{in}$ and accumulator width $w_\text{acc}$: $$ \text{Max samples before overflow} = \frac{2^{w_\text{acc}}}{2^{w_\text{in}}} = 2^{w_\text{acc} - w_\text{in}} $$
Example: 16-bit input, 48-bit accumulator → $2^{32}$ = 4.3 billion samples headroom.
Mathematical background
In the $z$-domain, each independent accumulator has transfer function:
$$ H_i(z) = \frac{1}{1 - z^{-1}}, \qquad i = 0, 1, \ldots, N-1 $$
This represents a discrete-time integrator with infinite DC gain. Overflow behavior depends on the ratio of accumulator to input bit widths.
Timing
The HLS-generated IP has a fixed latency of 3 clock cycles:
| Property | Latency (clock cycles) |
|---|---|
| Accumulator Full (TM) | 3 |
Total system delay: T_delay = 3 × T_CLK.
Typical use cases
- Multi-channel charge integration (particle detectors)
- Parallel energy measurement in spectroscopy
- Per-channel event counting
- Time-multiplexed pulse-height analysis
- Independent integrators for N-channel ADC arrays
Waveform example
Example with TM Factor = 4, Input = [1, 2, 3, 4, 1, 2, 3, 4, …].
Note: Each TM lane accumulates independently with 3 cycles latency.